A CMOS Stacked-FET Power Amplifier Using PMOS Linearizer with Improved AM-PM
- Author: Kim Unha, Woo Jung-Lin, Park Sunghwan, Kwon Youngwoo
- Organization: Kim Unha; Woo Jung-Lin; Park Sunghwan; Kwon Youngwoo
- Publish: Journal of electromagnetic engineering and science Volume 14, Issue2, p68~73, 00 June 2014
A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a 0.18-μm silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance (
Cgs) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than —40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.
CMOS , Linear , Power Amplifier (PA) , Stacked-FET , W-CDMA
Power amplifier (PA) is a key component in mobile handsets, but designing PA is still challenging because high efficiency as well as high linearity is demanded without any compromise for 3G/4G mobile standard applications. For this reason, high performance devices, such as GaAs HBT/HEMT, have mostly been employed for commercial PA fabrication. On the other hand, the CMOS PA has been widely researched to take advantage of its low cost and high integration capability. The weaknesses of the CMOS device/process (e.g., low breakdown voltage and no substrate via hole to the ground) have been overcome by using power combining techniques such as the stacked field-effect transistor (FET) and transformer-based differential cascode structures. Watt-level power amplification has thus been achieved in recent years [1-3]. However, the nonlinear characteristics of the CMOS device have prevented the CMOS PA from being used in actual 3G/4G handset PA applications where stringent linearity is required.
To enhance the linearity of a CMOS PA, several linearization techniques have been proposed. The use of a variable capacitor at the common-gate (CG) FET and envelope-reshaped gate bias technique effectively improved the PA linearity [2,3]. As explained in [4,5], one of the major nonlinearities of a CMOS device comes from the gatesource capacitance (
Cgs) of the common-source (CS) amplifier. This nonlinearity can be compensated using a PMOS device with opposite Cgsvs. Vgsbehavior to NFET . However, the use of a PMOS device at the gate of the mainstage causes capacitance overload. Since the overloaded capacitance makes the gate impedance very low, high-Q interstage matching cannot be avoided, which can impact the gain and efficiency as well as the bandwidth, as discussed in . In multi-stage PA design, the nonlinearities from the preceding (driver) stage as well as the main-stage should also be compensated. In , the nonlinearity from the driver-stage was not compensated but avoided by supplying high quiescent current to the stage, which may result in efficiency degradation.
In this work, a highly linear and efficient watt-level CMOS PA is implemented using an integrated PMOS linearizer for low-band UMTS Tx applications. The problem described above is resolved by employing a PMOS linearizer with optimized AM-PM at the input of the driver-stage, thereby compensating the composite nonlinearity coming from the two amplifiers. In this paper, the detailed circuit design of the proposed linear PA is presented in Section II, followed by the fabrication and measurement results of the PA in Section III.
Fig. 1 shows a schematic of the proposed linear CMOS PA. It is based on a two-stage single-ended stacked-FET amplifier design , and is targeted to obtain an output power (
Pout) of more than a watt using VDD= 4 V for handset applications. Thus, the optimum load impedance ( Ropt) is designed to be 6 Ω, which is smaller than that described in , where VDD= 6.5 V and Ropt= 11.5 Ω were used, because Poutcan be approximated to be Pout= VDD2 / Ropt. Due to smaller Ropt, the FET size should be increased to drive more RF current and avoid high knee voltage of the CMOS device . Thus, a quadruple stacked-FET with a gate width of 20 mm is adopted for main-stage ( M1 to M4) to attain sufficient voltage and current swings with margin. Each transistor is realized with a 2.5-V standard I/O NFET. According to the stacked-FET PA theory, optimum load impedances should be given for the intermediate FETs ( M1 to M3 in Fig. 1) as well as the top FET ( M4) for even distribution of RF voltage swing for each FET. Thus, five gate distribution capacitors in both stages ( C D2, C D3, C2, C3, and C4), which are the main design parameters for determining optimum loads of the intermediate FETs, are designed based on the analysis in . Even though the gate capacitors are properly designed, however, the load impedances of the intermediate FETs have sub-optimal values due to the excessive parasitic capacitances of a FET with large gate width. To cancel out the parasitic capacitances, three external drain-source Miller capacitors ( C M2, C M3, and C M4) are used and the efficiency can thus be improved . Fig. 2 shows the simulated load impedance of each FET of the driverstage and main-stage.
As described in [4,5], the nonlinear gate-source capacitance (
Cgs) of CS amplifier can be compensated using a PMOS, because a PMOS exhibits the opposite Cgsvs. Vgsbehavior to NMOS and thus the phase distortion is alleviated by flattening the capacitance slope . To resolve the problems mentioned in Section I, a PMOS linearizer is adopted at the gate of the driver-stage CS transistor, as shown in Fig. 1. This linearizer is composed of a PMOS ( MP), a dc block capacitor ( CP), and an inductor ( LP). Contrary to the phase linearizer in , LP is also used. The effective capacitance of the linearizer, CLIN, can be obtained by calculating the reactance sum of MP, CP, and LPas follows:
In this work,
CPis a DC blocker and is assumed to be far greater than CMP. As one can see from Eq. (2), CLIN is further increased as CMPis increased by adding LP, because CMP. and LPconnected in series tend to resonate out. Therefore, CLINcan be reconfigured to have a steeper (optimized) capacitance variation slope as a function of input power to additionally optimize the AM-PM of the overall PA.
Fig. 3 shows the simulated capacitance at the gate of the driver-stage and resultant AM-PM of the composite PA. The composite input capacitance (
CgN+ CLIN) at the driver- stage is not flat but has a positive slope to compensate for the phase nonlinearity of the following (main-stage) amplifier as well. By adopting LP, the capacitance variation slope can be reshaped to achieve optimal nonlinear Cgscompensation without using a large PMOS device. As shown in Fig. 3(b), the use of small / large LP(= 1.2 / 2.7 nH) lowers AM-PM distortion from 12° to 5.5° / 3.5°, respectively. Even if large LPfurther lowers the phase distortion near mid output power ( Pout) level, it causes early AM-PM compression at high Pout; thus, small LPwas used in this work. If LPis not used, the amount of AM-PM correction is limited to 7.5°, which is insufficient to meet the stringent W-CDMA linearity spec.
In addition, investigating the phase deviation by each FET of both stages is worthwhile. Fig. 4 shows the simulated drain voltage phase deviation of each FET. Contrary to the result without a linearizer, the phase of driver-stage using the linearizer becomes more pre-distorted, and then the signal is delivered to the main-stage. The phase deviation slope by the main-stage is the opposite direction to the input signal, and thus the resultant AM-PM is improved. Note that the stacked-FET structure is capable of self-phase compensation, because the CS amplifier and CG amplifier have the opposite phase characteristics . Fig. 5 shows the simulated DC gate-source bias of each FET, where no significant difference is observed between the PAs with and without linearizers.
The designed linear PA was fabricated using a 0.18-μm silicon-on-insulator (SOI) CMOS process with high-resistivity substrate (
ρ= 1 kΩ ۰ cm). All the MOSFETs have a gate-length of 0.32-μm and an oxide thickness of 52 nm, which is originally targeted for standard 2.5-V I/O operation. The PA is based on a two-stage amplifier design, and the gate-widths of a single FET for the driver-stage and main-stage were chosen to be 2 and 20 mm, respectively. The capacitances of five gate capacitors for CG-FETs, C D2, C D3, C2, C3, and C4, are 6, 2, 32, 12, and 8 pF, respectively. Three Miller capacitors, C M2, C M3, and C M4, have values of 3, 6, and 10 pF, respectively. The source degeneration effect of this PA was minimized by using multiple bond-wires. Also, a bond-wire is used for LP(in Fig. 1) implementation and optimization. The fabricated SOI CMOS IC is shown in Fig. 6, and its die size and thickness are 1.6 mm × 0.6 mm and 150 μm, respectively. It was mounted on a 400-μm-thick FR4 substrate ( εr= 4.6, tan δ = 0.025), where an off-chip LC network was used for output matching.
The implemented PA module was tested under the 3GPP uplink W-CDMA signal (Rel’99) at 836.5 MHz and a supply voltage of 4 V. The idle current is 75 mA. Prior to the W-CDMA test, the nonlinear characteristics of the PA were measured using single-tone (continuous wave [CW]) and two-tone signals. Fig. 7 shows the measured AM-AM and AM-PM characteristics using a CW signal. The AM-PM deviation of the linearized PA was reduced from 11.5° to 6°, which is close to the simulation result. Fig. 8 shows the two-tone third-order inter modulation distortion (IMD-3). By employing the linearizer, the linear output power meeting IMD3 = -30 dBc is extended.
The measurement results of power gain, power-added efficiency (PAE), and adjacent channel leakage ratio (ACLR) using W-CDMA signal are plotted in Fig. 9. The PA showed a power gain of higher than 27 dB and ACLR better than -40 dBc up to the output power of 27.1 dBm. Output powers / PAEs meeting ACLRs of -40 dBc and -36 dBc were 27.1 dBm / 45.6% and 27.7 dBm / 48.3%, respectively. Compared to the reference PA without a linearizer, which showed ACLR of -36 dBc and PAE of 38.5% at
Pout= 25.7 dBm, output power and PAE were improved by 2 dB and 9.8%, respectively. The linearization effect of the PA under the W-CDMA condition was validated by measuring the dynamic AM-AM and AM-PM. Fig. 10 shows the dynamic characteristics of the PA at Pout= 27 dBm. Compared to the reference PA, the proposed PA showed improved flatness in terms of gain and phase.
The performance of the recently reported W-CDMA PAs is summarized in Table 1 for comparison. The linearity and efficiency of the proposed PA is favorable among the reported PAs. Its performance is also comparable to the Ga-As-based PA .
A linear stacked-FET PA module has been implemented using SOI CMOS technology for W-CDMA handset applications. The gate-source capacitance nonlinearity of a common-source amplifier is compensated by employing a PMOS linearizer with optimized phase (capacitance) slope at the gate of the driver-stage transistor. Thus, the AM-PM is improved while avoiding capacitance overloading effect at the main-stage. The fabricated PA showed PAE of 45.6% and meets the UMTS linearity requirement with margin (< -40 dBc versus system spec of -33 dBc) at
Pout= 27.1 dBm. The performance of the PA is favorably comparable to that of GaAs-based PAs.
[Fig. 1.] Schematic of the proposed 2-stage linear CMOS stacked-FET power amplifier.
[Fig. 2.] Simulated load impedances of the main-stage and driver-stage FETs as a function of input power.
[Fig. 3.] Simulated results: (a) capacitance at the gate of the driver-stage as a function of output power, (b) AM-PM characteristics of the 2-stage stacked-FET power amplifier.
[Fig. 4.] Simulated drain voltage phase deviation of each FET: (a) Without linearizer and (b) with linearizer.
[Fig. 5.] Simulated DC gate-source bias of each FET: (a) without linearizer and (b) with linearizer.
[Fig. 6.] Chip photograph (size=1.6 mm × 0.6 mm).
[Fig. 7.] Measured AM-AM and AM-PM characteristics of the power amplifier using continuous wave signal.
[Fig. 8.] Measured third-order intermodulation distortion (IMD3) (tone spacing =4 MHz). ACLR = adjacent channel leakage ratio.
[Fig. 9.] Measured W-CDMA results: (a) Gain and power-added efficiency (PAE) and (b) adjacent channel leakage ratio (ACLR).
[Fig. 10.] Measured dynamic AM-AM and AM-PM characteristics at Pout = 27 dBm using W-CDMA signal.
[Table 1.] Performance comparison of recently reported W-CDMA CMOS power amplifier