Three-dimensional (3D) integrated-circuits (ICs) have better performance and energy efficiency, and a smaller footprint in electronic systems than two-dimensional (2D) ICs because of their smaller form factor due to 3D stacking and 3D interconnections . Compared with the currently available through-silicon via (TSV)-based 3D ICs , the monolithic 3D IC (M3IC) [3-12], in which each circuit layer is thin and is fabricated directly over the previous circuit layers on the same substrate, is a promising technology that enables ultrafine-grained vertical integration of devices and interconnections with the conventional monolithic inter-tier vias (MIVs) to connect the various layers.
There have been extensive studies of process, device, and circuit technologies for the M3IC [3-12]. SRAM and inverters utilizing dynamic threshold voltage (
In this paper, the electrical coupling between the stacked top/bottom FETs in two types of monolithic 3D inverter (M3INV), of which one includes a metal layer (ML) in the bottom tier and the other does not include a ML, will be systematically investigated using a 3D device simulator. Device characteristics of the two types of M3INV will be surveyed in terms of electrical coupling between the stacked top/bottom FETs (Section II). Next, the regime of the sizes and materials of the ILD, as well as the doping concentration and length of channel where the stacked FETs are coupled will be studied (Section III). Finally, Section IV will conclude this paper.
II. DEVICE CHARACTERISTICS OF THE M3INV
Fig. 1 shows the schematics of two examples of types of M3INV structure. Fig. 1(a) and (b) show Structure A [9,10], which includes the MLs between the top and bottom tiers and Structure B [3,6], which excludes them, respectively. Fig. 1(c) shows the cross-section of A-A′ in Structure A shown in Fig. 1(a). The cross-section of A-A′ in Structure B is the same as that shown in Fig. 1(c) except that MLs (Part A) and contacts (Part B) would be added. Here
[Fig. 1.] Schematics of two types of monolithic 3D inverter cells. (a) 3D schematic of Structure A with a metal layer in the bottom tier, (b) 3D schematic of Structure B without the metal layer, and (c) cross-section of A-A′ in Structure A shown in Fig. 1(a). ML, C, G, D, and S denote the metal layer, contact, gate, drain, and source, respectively. Materials in the structure and doping concentration in the silicon body are denoted by color.
Fig. 2 shows the DC/AC coupling between the bottom and top MOSFETs with
[Fig. 2.] (a) Inds-Vngs characteristics (linear and logarithmic), (b) transconductance (gm = dInds/dVngs), and (c) capacitance (Cngng, Cnsng, Cdng, Cpgng) of the top transistor in the M3INV cells (Structure A and B) as shown in Fig. 1(a) and (b). Symbols and lines denote Vpgs = 0 and -1 V, respectively. Empty and filled symbols denote Structure A and B, respectively. Here, Lg = 30 nm, TSi = 6 nm, Tox = 1 nm, TILD = 10 nm, Nd (Na) = 1015 cm-3, and Vds = 0.1 V. f = 1 MHz is applied for AC characterization. The subscripts nds, ngs, pgs, ngng, nsng, dng, and pgng denote drain-to-source of the NMOSFET, gate-to-source of the NMOSFET, gate-to-source of the PMOSFET, gate-to-gate of the NMOSFET, source-to-gate of the NMOSFET, drain-to-gate of the NMOSFET, gate of the PMOSFET-to-gate of the NMOSFET, respectively.
In this paper, the electrical coupling of the top NMOSFET will be quantified when the gate of the bottom PMOSFET is biased as two different voltages (0 and –1 V).
Empty and filled symbols denote Structure A and B, respectively, and symbols and lines denote
III. DEVICE COUPLING IN THE M3INV
Under what geometry or process conditions may the electrical coupling between the bottom and top MOSFETs be neglected? In order to investigate the coupling effect in three types of Structure B, the threshold voltage shift (
[Fig. 3.] (a) Threshold voltage shift and (b) voltage shift of transconductance (gm) and transcapacitance (Cngng) of the top transistor in the M3INV cell (Structure B) as shown in Fig. 1(b). Here, Nd (Na) = 1015 cm-3 and Vds = 0.1 V. Frequency f = 1 MHz is applied for AC characterization.
[Fig. 4.] Threshold voltage shift of the top transistor in the M3INV cell (Structure B) as shown in Fig. 1(b). (a) Material dependence in IML at TILD = 10 and 50 nm, and (b) doping concentration dependence in the silicon channel at TILD = 10 nm. Here Vds = 0.1 V.
Figs. 4(a) and (b) show
In Fig. 4(a), as
Fig. 5 shows
[Fig. 5.] Threshold voltage shift versus side-wall length of the top transistor in the M3INV cell at different TILDs. Here Lg = 30 nm and Vds = 0.1 V.
In this paper, we investigated the electrical coupling between the stacked top/bottom FETs in the M3INV. To investigate the coupling between the stacked devices, the drain-source currents versus the gate voltage of the bottom FET in the M3INV were simulated using a 3D device simulator with varying channel length, thickness of the ILD, material of the ILD, doping concentration in the channel, and side-wall length. When the doping concentration was below 1016 cm-3 and the side-wall length was below 20 nm, the threshold voltage shifts are almost constant in all of the three types of Structure B. The interaction between the stacked MOSFETs can be neglected in the M3INV with