Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage (VT) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.
The scaling of conventional planar flash memory is expected to end beyond the sub-20 nm technology node due to concerns about lithography, the coupling ratio, and the crosstalk interface. Future memory requires faster program/erase speed, longer data retention, and higher storage capacity, at a lower cost. SONOS flash memory devices have been considered the most promising candidate for implementing low-voltage and high-density nonvolatile semiconductor memory [1]. However, short channel effects (SCEs) become apparent as the memory cell is scaled down. To solve the SCE problem, various 3D structures for SONOS devices have been reported [2,3]. In particular, nanowire transistors have generated much recent research interest [4-7] because of their potential to replace conventional planar structures in scaling CMOS devices to gate length of 10 nm or less. With the impending tunneling limit of gate oxides at a thickness of 1 nm or slightly less, it is difficult to scale bulk MOSFETs to gate lengths of less than 20 nm with acceptable SCEs [8]. Nanowire transistors, which are basically gate-all-around devices, offer superior electrostatic control of the channel to suppress SCEs. This paper reports the fabrication of SiNW and planar SONOS flash memories, and and analysis of the electrical characteristics. To uncover the reason for good SCE immunity in SiNW SONOS devices, both devices were examined with 3D TCAD simulations.
A schematic of the SiNW gate-all-around (GAA) SONOS flash memory device and its process flow are shown in Fig. 1. A p-type (100) bulk wafer was used as the starting material. One distinctive feature in forming SiNW from bulk Si is the one-step etching route to pattern the SiNW and to isolate the adjacent FETs. A photolithography process using 0.18 μm technology was employed to define the SiNW. To achieve a minimum feature size for the SiNW, photoresist ashing, in part by oxygen plasma, was performed as described in another study [9]. Afterwards, the 180- nm line width was reduced to 30 nm. In the one-step etching route, in-situ generated CF4-based polymer begins to passivate the exposed Si surface during reactive ion etching (RIE) through the Bosch process [10].
In this process, isotropic etching is used exclusively to completely separate the SiNW from the bulk substrate. Therefore, enhanced reproducibility can be expected. Afterward, sacrificial oxidation was employed to alleviate etching damage. Next, ONO layers were deposited with thickness of 4/8/12 nm using silicon nitride (Si3N4) as the trapping layer. Additionally, an n+ in-situ doped poly-silicon layer was deposited to surround the SiNWs to fabricate the gate electrode. To pattern the gate, photoresist ashing was also used, and a gate length of 25 nm was ultimately achieved. 2-nm-thick oxide spacers were then formed for the subsequent formation of the source and drain (S/ D). After patterning the gate, the S/D was doped with arsenic, and the dopants were activated using rapid thermal annealing (RTA) at 1,000℃ for 3 sec. Finally, forming gas annealing was applied. Fig. 2 shows a cross-sectional transmission electron microscopy (TEM) image of the 25-nm gate length (
advanced multidimensional simulator capable of simulating the electrical, thermal, and optical characteristics of silicon-based and compound semiconductor devices.
Figure 3 shows the measured program/erase characteristics of the fabricated SiNW SONOS flash memory (
Figure 4 shows the experimental results of the gate voltagedrain current (VG-ID) measurements in the fabricated SiNW and planar SONOS devices with a 25 nm
To understand the origins of the excellent performance of SiNW SONOS devices, simulations were performed using a commercial 3D TCAD tool. Figure 5 shows the overall structure of the SiNW and planar SONOS devices. The simulation results are similar to the experimental data, as shown in Fig. 6. Compared with planar SONOS devices, SiNW SONOS devices show excellent SCE immunity, with good DIBL and SS performance.
The simulated
Figure 8 shows the results of the TCAD simulation of the electric field distribution of planar and SiNW SONOS flash memory devices. The electric field of the junction area is significantly reduced in the SiNW structure, as indicated with red circles.
The fabrication of silicon nanowire (SiNW) silicon-oxidenitride- oxide-silicon (SONOS) flash memory devices and the analysis of their electrical characteristics have been described. Compared with planar SONOS devices, SiNW SONOS devices have good P/E characteristics and show excellent SCE immunity due to enhanced gate controllability. In addition, the SiNW SONOS devices exhibit improved SCE immunity in accordance with the decrease in nanowire width. This is known to be due to the fully depleted mode operation as the nanowire becomes narrower. To uncover the reason for good SCE immunity in SiNW SONOS devices, both devices examined with TCAD simulations. The results show that the electric field of the junction area is significantly reduced in the SiNW structure.