Complementary metal-oxide semiconductor (CMOS) technology scaling has been enabling higher integration capacity in very largescale integration (VLSI) designs. Over the last few years,devices at 32 nm have been manufactured and the deep sub-micron/nano range of below 10 nm is foreseen to be reached in the near future as technology continues to scale down. In the 32 nm technology era, the leakage current has substantially increased,and the sensitivity to process variations in manufacturing is considered to be almost unavoidable. Due to the lower power supply and the smaller node capacitance, the amount of charge stored on a circuit node is becoming increasingly smaller, thus making circuits more susceptible to spurious voltage variations caused by externally induced phenomena such as cosmic ray neutrons and α-particles [1]. Therefore, robust CMOS circuitsdesign techniques is becoming crucial in the nanoscale era.

Technology boosters such as strain have helped the continuation of CMOS historic performance trend up to 45 nm node. As device physical gate length is reduced to below 25 nm at/beyond 65 nm technology node, various leakage currents and device parameter variationbecome the mostimportant considerations for device optimization. In fact, it can be argued that reduction of gate length below 25 nm may not offer the same advantage as short-gate devices had provided historically in terms of power and performance at the system level [2]. The major detractors are: the lack of a thin equivalent gate oxide (with low leakage current) for effective short channel effect control, the increasing contribution of the fringing parasitic capacitance to the total gate capacitance, and the rising contribution of the source/drain resistance to the total device on-resistance [3]. Moreover, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). It becomes more difficult to further improve device/circuit performance by reducing the physical gate length.

Therefore, new materials and devices have been investigated to replace silicon in nanoscaled transistors from the year 2015 and beyond. As one of the promising new devices, carbon nanotube FETs (CNTFETs) avoid most of the fundamental limitations for traditional silicon devices, due to their unique one-dimensional band-structure that suppresses backscattering and makes near-ballistic operation arealistic possibility [4-7]. A singlewalled CNT (SWCNT) can be visualized as a sheet of graphite,which is rolled up and joined together along a roll-up vector as shown in Fig. 1.

Depending on the chiral angle (roll-up vector or chirality vector), the CNT can be either semiconducting or metallic. By considering the indices (n, m) shown in Fig. 1, the nanotube is metallic if n = m or n-m = 3i where i is an integer. Otherwise, the tube is semiconducting. CNTFETs are the FETs that make use of semiconducting CNTs as channel material between two metal electrodes that act as source and drain contacts. The operation principle of CNTFET is similar to that of traditional silicon devices.As shown in Fig. 2, this three (or four) terminal device consists of a semiconducting nanotube, acting as conducting channel,bridging the source and drain contacts. The device is turned on or off electrostatically via the gate. Despite several serious technological barriers, CNTFETs with their small feature size and high-current capability show a potential for performance improvement compared with CMOS transistors.

The CV/I performance of an intrinsic CNTFET is 13 times better than the CV/I performance of a bulk n-type MOSFET because the CNTFETs effective gate capacitance of one CNT per gate is about 4% compared to bulk CMOS and the driving current ability of each CNT is about 50% of a bulk n-type MOSFET with minimum gate width (48 nm) at a 32 nm node (due to the ballistic transport nature of a CNT). Moreover due to the similar behavior and the current driving capability of a pFET compared to those of anFET, the performance improvement of a pFET over a PMOS is better than the one of a nFET over a NMOS. Even though a CNTFET has a leakage current in the off-state, this leakage current is controlled by the full band gap of the CNTs and the band to band tunneling; this is less than for a MOSFET [8,9].

The expected (optimistic) performance advantage of a CNTFET(as described previously) is unlikely to be achievable in a real device and will be significantly degraded for the CV/I (6 times for a nFET and 14 times for a pFET) due to device/circuit non-ideal conditions. These non-ideal conditions include the series resistance of the doped source/drain region, the Schottky barrier (SB)resistance at the metal/CNT interface, the gate outer-fringe capacitance and the interconnect wiring capacitance. However, the need for low power consumption and high operating frequency has resulted in geometry and supply scaling with a significant increase in operating temperature for a device. With these scaling features, the effects of systematic and random variations in process, supply voltage, and temperature (PVT) may cause an

inconsistent delay and increase in leakage to appear even in low power circuits, thus becoming one of the major challenges in nanoscale devices. Therefore, to measure the actual performance of a CNTFET compared to a MOSFET, it is necessary to compare performance at a circuit level under different conditions. In this paper, logic gates and benchmark circuits are designed at 32 nm for both CNTFET and CMOS technologies to assess the advantages of combinational logic gates using CNTFET; delay, power,power delay product (PDP), leakage current and frequency response are simulated and compared [8-10].

After the performance assessment of CNTFET based combinational logic gates, ternary logic gates is investigated as a part of combinational gate design to take advantage of the CNTFET technology.In a CNTFET, the threshold voltage of the transistor is determined by the diameter of the CNT. There- fore, a multithreshold design can be accomplished by employing CNTs with different diameters (and, therefore, chirality) in the CNTFETs. A resistive-load CNTFET-based ternary logic design has been proposed in [11]. However, in this configuration, large OFF-chip resistors(of at least 100 MΩ values) are needed due to the current requirement of the CNTFETs. The design technique proposed in this paper relies on [12] and eliminates the large resistors by employing active load with P-type CNTFETs in the ternary logic gates. Ternary logic (or three-valued logic) has attracted considerable interest due to its potential advantages over binary logic for designing digital systems. For example, it is possible for ternary logic to achieve simplicity and energy efficiency in digital design since the logic reduces the complexity of interconnects and chip area. The multivalued logic design based on multithreshold CNTFETs is assessed and compared with existing multivalued logic designs based on CNTFETs in this paper.

Another type of digital circuits required to build a digital system is sequential element such as latch or flip-flop to store data for pipeline structure. CMOS storage elements, such as CMOS memories and latches, usually include a data storage circuit or circuit element, which is capable to hold one bit of binary information.The storage cell also includes a data access device, for example, a pass gate transistor for static random access memory(SRAM) cell, or a transmission gate for latch. The data access device allows or disallows data read or write from and to the storage circuit depending on the state of the control signal on the control node of the access device. Additional circuit elements may be used to improve environmental tolerance and to accommodate a variety of functions in a single memory cell [13]. As device density increases, alarger fraction of chip area is devoted to the onchip memory modules, because on- chip memory helps improve the micro-architectural performance of a microprocessor. Several of the latest processor designs showed that around 50% of the chip area was occupied by caches [14]. Meanwhile, latches and D flip-flops, which are the basic building blocks of the sequential circuits, also take a large area of the latest chips. This paper studies on the analysis and design of robust storage elements in both 32 nm CMOS technology and novel CNTFETs for comparison

and feasibility study.In this paper,the feasibility is studied for the robust design of two major storage elements (latch and memory cell) in modern integrated circuits.

Section 2 discusses and assesses the CNTFET based combinational logic gates in comparison with CMOS nanoscale combinational logic gates, and ternary logic gates are proposed and its performance is studies in Section 3. Section 4 presents the memory elements design and their performance in comparison with their nanoscale CMOS counterpart, followed by conclusion in Section 5.

To measure the actual performance of a CNTFET compared to a MOSFET, it is necessary to compare performance at a circuit level under PVT variations. In this paper, logic gates and benchmark circuits are designed at 32 nm for both CNTFET and CMOS technologies; delay, power, PDP, leakage current and frequency response are simulated and compared [8-10].

For comparing the performance of CNTFETs with MOSFETs at circuit level, the inverter as a fundamental logic gate is considered first; the inverter is designed with minimal width and a number of tubes in 32 nm technology. For Si CMOS, a PMOS/NMOS ratio between 2 and 3 is used for compensating the difference in mobility between PMOS and NMOS. In this paper, a 3 to 1 (PMOS:NMOS) ratio is used when designing the inverter because the voltage transfer characteristic (VTC) of the MOSFET inverter shows a more symmetrical shape in the center of the logic threshold voltage (VDD/2) for a ratio of 3 in 32 nm as shown in Fig. 3.

However, for the CNTFET case, a 1 to 1 (pFET:nFET) ratio is used because the nFET and the pFET have almost the same current driving capability with same transistor geometry [8]. Figure 3 shows that the VTC of the CNTFET also has a symmetrical shape at a 1 to 1 (pFET:nFET) ratio. Even though the current in a CNT is smaller than theminimum sized MOSFET (at 32 nm technology), a CNTFET has a steeper curve in the transition region due to the higher gain. This contributes to a 22.5% improvement in noise margin (NM), and this progressed performance is preserved under a decrease in power supply voltage as shown in Fig.. 4 In this paper, the ratio value used for the inverter is also uti-

lized when designing more complex logic gates and benchmark circuits and used to determine the width and number of tubes of the CNTFET. To determine the PMOS/NMOS ratio for CMOS, the transistor width (W) of a MOSFET is modified; however in a CNTFET, the number of CNTs is changed because a CNTFET uses CNTs for the conducting channel between the source and drain. Therefore, when the width of the CNTFET is changed, by implication the number of tube is also changed.

In this section, different metrics are utilized to compare CNTFET and CMOS logic gates at 32 nm features size. The design performance metrics used to compare the two different technology based logic gates are PDP, leakage power, PVT variation, and frequency response.

2.2.1 Power delay product

Due to the increased demand for high-speed, high-throughput computation, and complex functionality in mobile environments,reduction of delay and power consumption is very challenging.MOSFET and CNTFET can be compared using the PDP as metric. Table 1 shows the delay, power, and PDP of logic gates in 32 nm MOSFET and 32 nm CNTFET technologies; the PDP of the 32 nm MOSFET is about 100 times higher than that of the 32 nm CNTFET.

2.2.2 Leakage power

As process dimensions shrink further into the nanometer ranges, traditional methods for dynamic power reduction are becoming less effective due to the increased impact of static power [15]. In general, leakage power is different depending on the applied input vector. Figure 5 shows the maximum and minimum leakage power for 32 nm MOSFET and CNTFET based logic gates. The maximum leakage power of the MOSFET-based gates is 75 times larger than for CNTFET gates. The minimum leakage power of the MOSFET is about three times larger than for CNTFET. Figure 5 also shows that the maximum leakage power shows a similar trend for both CNTFET and MOSFETbased gates, while the minimum leakage power shows somewhat different trends, because the stack effect is reduced in CNTFET circuits.

2.2.3 Frequency response

For establishing the frequency response, AC simulation has been performed for both the MOSFET and CNTFET inverters.The results are given in Fig. 6, where the CNTFET inverter shows nearly 3dB more voltage gain and 3 times higher 3dB frequency(f_3dB) than the MOSFET inverter, thus confirming its superiority in terms of this metric.

2.2.4 PVT variations

With technology scaling, the effects of systematic and random

variations in PVT have led to inconsistent delay and leakage in low power circuits, thus becoming a major obstacle for device scaling. Significant levels of process variations affect technology scaling beyond 90 nm, and they are changing the design environment from a deterministic to a probabilistic one. Moreover,the requirement of low power relies on supply voltage scaling,making voltage variations a significant challenge. The quest for increase in higher operating frequencies has resulted in significantly high junction temperature and within-die temperature variation [10,16]. Therefore, the possible performance degradation due to PVT variations has become a major criterion in assessing the performance of a new technology.

2.2.4.1 Process variation

When investigating physical process variations, among them channel length and widths are considered for CMOS MOSFET.

However, CMOS and CNTFET have different characteristics.The current change in a MOSFET is about ±30% (±13%) for a±10% change in length (width) at a gate voltage of 0.9 V while the current change in a CNTFET is below ±0.5%. However when the diameter of the CNTFET is changed by ±10%, the current change in a CNTFET is about ±17% as shown in Fig. 7. Therefore for a CNTFET, the diameter variation is more important because a CNTFET is more sensitive to diameter variation than

length and width variations. Based on this observation, the PDP and leakage of a CNTFET are computed and shown in Figs. 8 and 9, respectively. When the diameter of a CNTFET is changed,then the PDP changes too. Figure 9 shows that the maximum leakage power increases when the diameter is increased. Also note that the threshold voltage and diameter of a CNTFET are determined based on the chirality of the CNTsused in this type of transistor.

2.2.4.2 Voltage variation

The reduction in power consumption due to voltage scaling is also confronted with the increased sensitivity to voltage variations; this is a major concern to assess the performance of a new technology such as CNTFETs. Figures 10 and 11 show the PDP for 32 nm MOSFET and CNTFET logic gates, respectively when the supply voltage is decreased until the gate stops functioning. These figures show that the inverter and the other logic gates op-

erate until the supply voltage decreases to 0.5 V and 0.6 V, respectively. Even though the PDP is changed depending on the supply voltage, this change is more or less the same as the change in PDP for the MOSFET logic gates; hence, the overall PDP of the CNTFET-based gates is significantly lower than for the MOSFET-based gates.

2.2.4.3 Temperature variation

As the circuit speed increases, a larger power consumption is often encountered, thus resulting in more heat at chip level. Circuits with an excessive power dissipation are more susceptible to run-time failures and account for serious re- liability problems [10,16]. Figures 12 and 13 show that the PDP of the MOSFET gates increases with temperature; however, the PDP of the CNTFET logic gates is constant. Moreover, the maximum leakage power of the MOSFET gates increases linearly with temperature, while for the CNTFET-based gates this increase is exponential.

Few combinational circuits (such as a 4 stage inverter chain, a 2:4 decoder, a 4:16 decoder, the ISCAS-85 Benchmark Circuit C17, a 1-bit full adder, a 3-bit Ripple Carry Adder, and the ISCAS-85 Benchmark Circuit 74182) have also been evaluated. The average delay and power consumption of the 32 nm MOSFET circuits is about 10 times and 100 times higher than those of the 32 nm CNTFET circuits respectively; these results confirm the findings found in the previous sub-sections for the CNTFET and MOSFET logic gates. Moreover, it shows that indeed CNTFET based design offer significant improvements over MOSFETbased designs.

Digital computation has been performed on two-valued logic, i.e., there are only two possible values (0 or 1, true or false) in the Boolean space. Multiple-valued logic (MVL) replaces the classical Boolean characterization of variables with either finitely or infinitely many values such as ternary logic [17] or fuzzy logic [18]. Ternary logic (or three-valued logic) has attracted considerable interest due to its potential advantages over binary logic for designing digital systems. For example, it is possible for ternary logic to achieve simplicity and energy efficiency in digital design since the logic reduces the complexity of interconnects and chip area [19]. Furthermore, serial and serial-parallel arithmetic operations can be carried out faster if the ternary logic is employed. Extensive research on design and implementation of ternary logic using CMOS can be found in the technical literature [19,20]. Chip area and power dissipation can be reduced by more than 50% using an efficient MVL implementation for a signed 32-bits multiplier compared to its fastest binary counterpart [11]. MVL modules have been inserted into binary logic ICs to enhance the performance of CMOS technologies [21].

There are two kinds of MVL circuits based on MOS technology,

namely the current-mode MVL circuits and the voltage- mode MVL circuits. Voltage-mode MVL circuits have been achieved in multi-threshold CMOS design [22]. In a CNTFET, The threshold voltage of the transistor is determined by the diameter of the CNT. Therefore, a multi-threshold design can be accomplished by employing CNTs with different diameters (and, therefore, chirality)in the CNTFETs. A resistive-load CNTFET-based ternary logic design has been proposed in [11]. However, in this configuration,large OFF-chip resistors (of at least 100 MΩ values) are needed due to the current requirement of the CNTFETs. The design technique proposed in [23] relies on [12] and eliminates the large resistors by employing active load with P-type CNTFETs in the ternary logic gates. In this paper, the multivalued logic design based on multi-threshold CNTFETs is assessed and compared with existing multivalued logic designs based on CNTFETs.

Ternary logic functions are defined as those functions having significance if a third value is introduced to the binary logic.In this paper, 0, 1, and 2 denote the ternary values to represent false, undefined, and true, respectively. Any n variable {X₁, . . .,X_n} ternary function f (X) is defined as a logic function mapping {0,1,2}ⁿ to {0, 1, 2}, where X = {X₁,...,X_n}. The basic operations of ternary logic can be defined as follows, where - denotes the arithmetic subtraction, the operations +, ●, and are referred to as the OR, AND, and NOT in ternary logic, respectively. The fundamental gates in the design of digital systems are the inverter, the NOR gate, and the NAND gate. The assumed logic symbols are shown in Table 2. The ternary gates are designed according to the convention defined by Eq. (1).

A general ternary inverter is an operator (gate) with one input x, and three outputs (denoted by y₀, y₁, and y₂) such that

Therefore, the implementation of ternary inverter requires three inverters, and they are a negative ternary inverter (NTI), a

standard ternary inverter (STI), and a positive ternary inverter (PTI), if y_o, y₁, and y₂ in (2) are the outputs [19]. The truth table of the three ternary inverters is shown in Table 3.

The ternary NAND and NOR are two multiple entry operators used in ternary logic. The functions of the two-entry ternary NAND and NOR gates are defined by the following two equations,respectively [20]:

The truth table for the ternary NAND and NOR gates is shown in Table 4.

CNTFETs utilize semiconducting SWCNTs to assemble electronic devices [24]. A SWCNT consists of one cylinder only, and the simple manufacturing process of this device makes it very promising for alternative to today’s MOSFET. A SWCNT can act as either a conductor or a semiconductor, depending on the angle of the atom arrangement along the tube. This is referred to as the chirality vector and is represented by the integer pair (n, m). A simple method to determine if a CNT is metallic or semiconducting is to consider its indexes (n, m): the nanotube is metallic if n = m or n-m = 3i, where i is an integer. Otherwise, the tube is semiconducting. The diameter of the CNT can be calculated based on the following [3,8,25]:

where a₀ = 0.142 nm is the interatomic distance between each carbon atom and its neighbor. The I-Vcharacteristics of the CNTFET are similar to MOSFET’s. The threshold voltage is defined as the voltage required to turnON transistor. The threshold voltage of the intrinsic CNT channel can be approximated to the first order as the half bandgap that is an inverse function of the diameter [3,8,25], i.e.

where a=2.49 angstrom is carbon to carbon atom distance, and V_π = 3.033 eV is the carbon π？π bond energy in the tightbonding

model, eis the unit electron charge, and D_CNT is the CNT diameter. As DCNTof a (19, 0) CNT is 1.487 nm, the threshold voltage of a CNTFET using (19, 0) CNTs as channels is 0.293 V from Eq.(6). As the chirality vector changes, the threshold voltage of the CNTFET will also change. Assume that m in the chirality vector is always zero, and then the ratio of the threshold voltages of two CNTFETs with different chirality vectors is given as:

Equation (7) shows that the threshold voltage of a CNTFET is inversely proportional to the chirality vector of the CNT. For example,the threshold voltage of a CNTFET using (13, 0) CNTs is 0.428 V, compared to a (19, 0) CNTFET with a threshold voltage of 0.293 V.

A CNTFET-based ternary logic design has been initially pro-

posed in [11]. It employs dual-diameter CNTFETs and resistors.However, two large resistors (usually 100 MΩ or greater) are required to implement the design, but their values are too large to be integrated into CNTFET technology. Lin et al. [23] proposed CNTFET-based STI design; the STI in Fig. 14 consists of six CNTFETs. The chiralities of the CNTs used in T1, T2, and T3 are (19,0), (10, 0), and (13, 0), respectively. From Eq. (5), the diameters of T1, T2, and T3 are 1.487, 0.783, and 1.018 nm, respectively. Therefore, the threshold voltages of T1, T2, and T3 are 0.289, 0.559, and 0.428 V, respectively from Eq. (6). The threshold voltages of T5, T6, and T4 are -0.289, -0.559, and -0.428 V, respectively. When the input voltage changes from low to high at the power supply voltage of 0.9 V, initially, the input voltage is lower than 300 mV. This makes both T5 and T6 turn ON, both T1 and T2 turn OFF, and the output voltage becomes 0.9 V, i.e. logic 2. As the input voltage increases beyond 300 mV, T6 is OFF and T5 is still ON. Meanwhile, T1 is ON and T2 is OFF. The diode connected CNTFETs T4 and T3 produce a voltage drop of 0.45 V from node n2 to the output, and from the output to n1 due to the threshold voltages of T4 and T3. Therefore, the output voltage becomes 0.45 V, i.e., half of the power supply voltage. As shown in Table 2, half V_dd represents logic 1. Once the input voltage exceeds 0.6 V, both T5 and T6 are OFF, and T2 is ON to pull the output voltage down to zero. The input voltage transition from high to low transition is similar to the low to high transition.

Simulation on these STIs has been performed by HSPICE using the CNTFET model of [3]. This HSPICE model of the CNTFET is described in more detail in [8,25]. The VTCs of the STI in Fig. 14 are shown in Fig. 15, which demonstrates that the proposed STI design provides a larger NM. That is a positive feature for low-power supply circuits. Furthermore, the proposed STI achieves a rail-to-rail output swing in contrast to the conventional STI design. In the HSPICE simulation, two STIs are cascaded as a ternary buffer. The average power consumption is the average power consumed by the two STIs, while the average delay is the average of the sum of four terms, i.e., the delay from 0 to 1, the delay from 1 to 2, the delay from 2 to 1, and the delay from 1 to 0. HSPICE simulation shows that the PDP of the proposed CNTFET-based STI is 6.08 × 10^？17 J, and the PDP of the STI in [11] is 2.07 × 10^？16 J. The proposed CNTFET-based STI achieves more than 300% performance improvement over [11] in terms of PDP.

As mentioned in the subsection 2.1, there are three inverters in the general ternary inverter system, which are NTI, STI, and PTI [19]. Figure 14 shows the proposed STI design. The NTI and PTI designs are shown in Fig. 16, where Fig. 16(a) shows the CNTFET-based NTI schematic diagram. The threshold voltage of T1 is 0.289 V, while the threshold voltage of T2 is -0.557 V. When the input voltage is below 0.3 V (i.e., logic 0), the output voltage is 0.9 V. As soon as the input voltage exceeds 0.3 V, T1 is ON and T2 is OFF, and the output voltage will be zero. For the CNTFET-based PTI shown in Fig. 16(b), the threshold voltage of T1 is 0.557 V and the threshold voltage of T2 is -0.289 V. Therefore, only when the input voltage is higher than 0.6 V, the output voltage is zero. The outputs of NTI and PTI correspond to y₀ and y₂, as given previously in Eq. (2). Figure 17 shows the symbols of NTI, STI, and PTI.

The ternary gates presented in this section can be used for designing ternary arithmetic circuits such as ternary adders and multipliers. As required for these circuits, a new design of the ternary decoder is presented in Fig. 18. The ternary decoder is a one-input, three-output combinational circuit and generates unary functions for an input x. The response of the ternary decoder to the input x is given by

where k can take logic values of 0, 1, or 2. The decoder consists of a PTI gate, two NTI gates, and a NOR gate, as shown in Fig. 18

The logic expressions of the ternary NAND and NOR gates are given in Eqs. (3) and (4). The circuits and symbols for the twoinput ternary NAND and ternary NOR are shown in Figs. 19(a) and (b), respectively. Each of these two gates consists of ten CNTFETs, with three different chiralities. They are essentially the same as their binary CMOS counterparts, except for the transistors of different threshold voltages. In these two gates, similar to the STI circuit of Fig. 14, the transistors with diameters of 1.487, 0.783, and 1.018 nm have threshold voltages of 0.289, 0.559, and 0.428 V, respectively, as established using Eq. (6). HSPICE simulation is confirmed the correctness of these designs with Tables 3 and 4.

One of the main advantages of ternary logic is that it reduces the number of required computation steps. Since each signal can have three distinct values, the number of digits required in a ternary family is log₃2 times less than required in binary logic. Therefore, if we consider an N-bit binary adder, then the corresponding ternary adder has [log₃ 2N] digits, where [x] represents the integer nearest to x and greater than x (i.e., the ceiling function).

A ternary half adder (HA) is then designed to verify the correctness of the proposed CNTFET-based design. The truth table of the ternary adder is given in Table 5 and the output equations for the HA can be derived from the Table 5 as

where A_k and B_k denote the output of the inputs A and B from the decoder shown in Fig. 18

The schematic diagram of the HA proposed in [26] is shown in Fig. 20. Two decoders generate the unary output signals for inputs A and B, while the logic gates compute the functions given by Eqs. (9) and (10). The so-called Tbuffer of Fig. 20 represents a level shifter and its logic function is given by

where in is the input of the T gate and Out is the output of the T gate.

The transient response of the ternary HA design based on CNTFETs is shown in Fig. .20. Simulation results are consistent with the truth table given in Table 5

The ternary logic achieves significant savings in PDP compared with the ternary logic family with resistors proposed in [11]. By replacing ternary gates with binary gates in the internal logic, the proposed design also achieves power and delay savings due to the reduced number of transistors in the binary gates. Note that by replacing the external resistors with transistors, a significant saving in area is also achieved. Therefore, the proposed ternary design is a fast and low-power solution to digital computation compared with the existing conventional ternary logic families, as well as the binary implementation. The simulation results confirm that the ternary logic based haf adder’s PDP is reduced by 90% compared with the existing logic families for arithmetic circuits [23], which implies that the ternary logic is a good solution to low power and high speed digital system design.

Design of fast and power efficient memory structures continues to be of the highest priority, and ballistic transport operation and low off current make the CNTFET a suitable device for high performance and increased integration density of SRAM design. Moreover, the MOSFET-like model of the CNTFET is likely to be scalable down to 10 nm channel length, thus providing a substantial performance and power improvement compared to the MOSFET model (with minimum channel length of 32 nm [3]). Therefore, a SRAM design implemented using CNTFETs requires a significantly smaller area than its CMOS counterpart. A resistive-load CNTFET-based SRAM cell has been proposed in [27]. However, large off-chip resistors (i.e. 100 MΩ) are needed in the configuration due to the current requirements of the CNTFETs. This resistive-load CNTFET-based SRAM cell design is modified with P-type transistors as active load to address this problem as proposed in this paper.

The use of transistors with multiple threshold voltages (i.e.a so-called multi-threshold design) is widely utilized in today’s CMOS circuits to improve performance. The threshold voltage can be changed by applying different bias voltage to the bulk terminal of the CMOS transistors. The threshold voltage of CNTFET is determined by the CNT diameter as described in the previous Section. Therefore, CNTFETs with different threshold voltages can be accomplished by growing CNTs with different diameters(chiralities). In this paper, a CNTFET-based SRAM cell design

with optimized threshold voltages is introduced, assessed, and compared to the CMOS implementation of the same cell.Different diameters (and therefore chirality) are utilized for the two types of CNTFETs (i.e. N or P). The optimum chirality is selected to achieve the best-combined performance in terms of stability,power consumption, and write time of the CNT-based SRAM cell.

Figure21(a) shows the conventional six-transistor (6T) SRAM cell configuration used as the core storage element of most register file and cache designs in CMOS. With today’s aggressive scaling, substantial problems such as power consumption and stability have already been encountered when the 6T SRAM cell configuration is utilized in CMOS at nanoscale ranges. In this paper, the 6T SRAM cell of Fig.21(a) is designed using CNTFETs (shown in Fig.21(b)) and its performance is assessed comprehensively with a newly proposed figure of merit denotes as “SPR”to compare stability, power dissipation, and write time with other existing SRAM cell designs. The basic design concept of the CNTFET-based memory has been proposed in [28], and this paper presents the actual design of the concept based on CNTFET technology addressing the realistic design challenges and issues such as performance, static NM (SNM), power consumption,and tolerance to PVT variations.

4.1.1 Read operation

Prior to the read operation, BL and BLB of Fig.21(b) are precharged to high level. When the wordline signal WL is high, the access transistors MN1 and MN2 are turned on, and the data stored in the SRAM is read. However, a read-upset problem is present during the read operation, and this may change the data stored in the SRAM cell. The read-upset problem can be described as follows. Assume that the cell is currently storing “1” so that q is “1” and nqis “0”. When WL is high, MN1 and MN2 are on and the voltage at node nqwill rise. An appropriate sizing ratio between MN4 and MN2 is required to limit the voltage at node nqto be lower than Vth such that the stored logic value does not change during the read operation. In the traditional CMOS design, the MN4/MN2 ratio should be greater than 1.28 for this requirement[15]. For the CNTFET SRAM design, simulations have been performed to establish the sizing ratio of MN4 and MN2. The gate and source of MN2 are connected to Vdd, and the gate of MN4 is also connected to Vdd as the voltage at q needs to be set to “1”. The right ratio of MN4/MN2 is found by running simulations for various MN4/MN2 ratios and gate lengths vs. the voltage rise at nq node. The transistor size ratio of the two CNTFETs is measured as the number of tubes in the two CNTFETs unlike MOSFET. The threshold voltage of the (19, 0) chirality CNTFET is 0.289 V. Therefore, the MN4/MN2 ratio should be kept greater than 0.5 to keep the voltage of nqbelow threshold voltage. However, for fair comparisons, the MN4/MN2 ratio used in this paper for the CNTFET SRAM design needs to be greater than 1.4 to control the low state voltage below the threshold voltage of the 32 nm MOSFET which is 0.18 V [29].

4.1.2 Write operation

During the write operation, the wordline WL is high to allow the data on bitlines BL and BLB to be written into the SRAM cell. For a successful write to a SRAM cell, the pull up transistor should not be too strong. Assume that the SRAM cell is storing “1”and it is required to write a new data “0” into the SRAM cell. The node q in Fig.21(b) is going to be low, so the pass gate MN1 must be significantly more conductive than the PMOS MP5. In the traditional CMOS design, the MP5/MN1 ratio should not be greater than 1.6 [15]. For CNTFET SRAM design, simulations have been performed to establish the size ratio between MP5 and MN1. The bias voltage on the gate of MP5 is kept below Vth, and the bias voltage on the gate of MN1 is Vdd. Simulations are run for various ratios and channel lengths. Any MP5/MN1 ratio of less than 1.6 can pull node q below 0.289 V, which is the threshold voltage of a CNTFET with (19, 0) chirality nanotubes. Similarly to the read operation, the MP5/MN1 ratio used in this paper for the CNTFET SRAM design needs to be less than 1 to ensure that the write voltage at node q is not higher than the threshold voltage of the 32 nm MOSFET (i.e. 0.18 V).

Therefore, for the dual-diameter CNTFET-based SRAM cell design, the transistor size ratios among the pull-up FET, the pulldown FET, and the access transistors are MP5/MN1 = 0.5 and MN4/MN2 = 1.5. P-type CNTFETs with one tube are used for MP5 and MP6, while n-type CNTFETs with three tubes are used for MN3 and MN4. The number of tubes used for MN1 and MN2 is two.

As the channel length of the CNTFET decreases to 32 nm or below, the drain current of the CNTFET decreases due to energy quantization in the axial direction. Phonon scattering in shortchannel devices further reduces the on-current [8]. The drain current of CNTFET decreases dramatically when the channel length is less than 20 nm. Therefore, by considering area and performance, a 20 nm gate length is chosen in this case for the design of the CNTFET-based SRAM cell.

As the distance between two adjacent tubes within the same device is 20 nm and the channel length chosen in this paper (as per previous discussion) is also 20 nm [3], the dimensions of the pull-up transistor MP5, the pull-down transistor MN3, and the pass gate transistor MN1 are 40/20 nm, 80/20 nm, and 60/20 nm, respectively (40/20 nm denotes the width to length ratio).

For a CMOS SRAM cell with a transistor length of 32 nm and similar circuit performance to the CNTFET SRAM cell proposed in this section, the widths of MP5, MN3, and MN1 are found to be 80 nm, 160 nm, and 120 nm, respectively. Therefore, there are two 80/32 nm PMOS transistors, two 160/32 nm NMOS transistors and two 120/32 nm NMOS transistors in the CMOS SRAM cell. Compared to the CMOS at 32 nm feature size, the CNTFETbased SRAM cell has two 40/20 nm P-CNTFETs, two 80/20 nm N-CNTFETs, and two 60/20 nm N-CNTFETs. These transistors are used in the next section to establish the best operation under the optimized threshold voltages for the dual-diameter CNTFETbased SRAM cell.

Since the threshold voltage of CNTFET can be controlled by adjusting tube’s diameter, the design of CNTFET based circuits with different threshold voltages is possible because CNTs can be grown with different diameters [11,30,31]. In this paper, Ntype and P-type CNTFETs use CNTs that have different chirality vectors for the best (optimized) performance. However, all Ntype CNTFETs use CNTs with the same chirality vector and all P-type CNTFETs use the same chirality vector as well (the dualdiameter arrangement is used for simplicity, although additional threshold voltages could also be utilized by using CNTs’ different diameters in the transistors).

A new index is defined for the CNTFET-based SRAM design,and it is given by the triplet (np, nn, m), where np and nn represent the first chirality vector “n” of the PCNTFETs and NCNTFETs, respectively, and m is the common second chirality vector“m” of the two CNTFETs [32,33]. For example, a SRAM cell with (16, 0) PCNTFETs and (19, 0) NCNTFETs is represented by the index triplet (16, 19, 0). The difference in chirality between N-type and P-type CNTFETs must also take into account the performance of the SRAM memory cell. As for CMOS SRAM, the threshold voltage of the pull-up P-type FETs (MP5 and MP6 shown in Fig.21(b)) have a close relationship with the SNM of the SRAM cell (the SNM is defined as the maximum value of DC noise voltage that can be tolerated by the SRAM cell without changing the stored bit [34]). The SNM is commonly used as a metric for static stability of a SRAM cell [35].

To investigate the SNM of the proposed dual-diameter CNTFET SRAM, extensive simulations have been performed on CNTFET SRAM cells with index triplets of (10, 19, 0), (13, 19, 0), (16, 19, 0), (19, 19, 0), and (22, 19, 0) for the transistors. Figure 22shows the simulation results of the read SNM of the SRAM cell at 0.9 V power supply and room temperature. For the 6T SRAM cell configuration in Fig. 21, the worst-case stability condition occurs when the cell is accessed for read operation, i.e. the read SNM is lower than the hold SNM. Simulation has shown that as the chirality vector of the PCNTFETs changes from (10, 0) to (22,0), then the SNM of the CNTFET SRAM is increased. As shown in Fig.22(a), the read SNM of the CNTFET SRAM is larger than for the CMOS SRAM at 32 nm feature size. Simulation has also been performed by changing the chirality vector of the N-type CNTFETs in the range from (10, 0) to (22, 0). As shown in Fig.22(b), the values of the read SNM of the CNTFET SRAM change little as the chirality vectors of the N-type CNTFETs change. Therefore,for best stability, the chirality vector of the PCNTFETs must be adjusted.

The stability of the SRAM cell can be increased by decreasing the absolute value of the threshold voltage of the pull-up transistor and controlling its chirality vector. However, there is a conflicting constraint between performance and stability. At a better ability to hold data, it is also harder to write new data into the SRAM cell, i.e. it takes more time to write new data. To find the optimum chirality for both PCNTFETs and NCNTFETs, both the SNM and the write time must be considered. Table 5 shows the SNM and the write time of the CNTFET SRAM cell with different threshold voltages of the PCNTFET at 0.9 V power supply and room temperature. Both the SNM and the write time increase with decrease of the absolute value of the threshold voltage of the pull-up transistor. For a highly stable and low delay design, a high SNM and a fast write time are desired. Therefore, the SNM is divided by the write time to find the best threshold voltage of the PCNTFET for both high SNM and fast write time. As shown in Table 5, when the threshold voltage of the PCNTFET is '0.343 V' for a (16, 19, 0) SRAM cell, the ratio between the SNM and the write time is the highest among those CNTFET SRAM cells listed in Table .5 Therefore, the (16, 19, 0) SRAM cell is selected for best overall performance. It is also shown in Table 5 that the ratio between the SNM and the write time for the CNTFET SRAM cell is significantly higher than for the CMOS SRAM cell, i.e. high stability is attained at a low write time.

A novel is required to comprehensively assess the performance as a function of delay, stability with respect to noise, and power

dissipation within a comprehensive metric. HSPICE simulations are performed using the Stanford CNTFET model [3] and the Berkeley Predictive 32 nm CMOS model [29] to compare the CNTFET and CMOS 6T SRAM cells. It has been shown in [35] that both the SNM and the static current noise margin (SINM) must be used to address the static stability of a SRAMcell. Therefore, SNM and SINM are multiplied together to yield a comprehensive figure of merit as thestatic power noise margin (SPNM). The PDP is an important and often used to measure and compare the circuits. It has been shown in articles [8,25] that the CNTFET has very high on/off current ratio compared with its CMOS counterpart. Therefore, the standby power of the CNTFET SRAM is significantly lower than for the CMOS SRAM. However, it is also important to address write power dissipation as the power dissipated by a memory cell during the write operation is higher than the power dissipated during the read operation due to the full swing charge and discharge on the bitlines during the write operation. Therefore, the PDP of the SRAM cell proposed in this paper is the product of the write power and the write delay.

The new comprehensive performance metric proposed in [36]

includes delay, stability, and power. It is given by dividing the SPNM by the PDP and this is referred to as the SPNM to PDP ratio (SPR). The SPR (in units of 1/secs) can be expressed as SPR =(SNM × SINM)/(write power × write delay) and provides a metric for high stability, low delay and low power in the operation of a memory cell. SPR is also versatile as it can be used to assess performance under different operational conditions, such as standby and write. Table 6 shows the SNM, SINM, write power, and write delay of the CMOS SRAM cell and the CNTFET SRAM cell at 0.9 V power supply and room temperature. As shown in Table 6, the CNTFET SRAM cell is designed to have the same write delay as the CMOS SRAM cell. The decrease of the write delay implies that it is easier to write data into a SRAM cell, thus making stability degrade. Also, the improvement in delay performance usually requires a larger transistor size, thus increasing power consumption. Therefore, to comprehensively assess performance as a function of delay and stability with respect to noise and power dissipation, a new metric must be used. The metric SPR provides such a metric for a SRAMcell in terms of delay, stability, and power.Table 6 confirms that the SPR of the CNTFET 6T SRAM cell is four times higher than its CMOS counterpart, hence attaining low power, high stability, and low delay within the comprehensive metric provided by the SPR under write conditions.

Systematic and random variations in process, PVT are posing a major challenge to nanoscale CMOS integrated circuits. Systematic variations in PVT are shared among all devices and have become a significant concern to the parametric yield in terms of energy and delay.

In CMOS process, random process variations often cause geometric variations in the gate (length, width, and thickness) as well as gate oxide thickness. In short channel devices, a variation in channel length also induces change in threshold voltage due to the drain-induced barrier lowering (DIBL) [37]. These variations still exist even in CNTFET. However, due to the cylindrical geometry, a variation in the gate oxide thickness that strongly affects the drive current and capacitance of CMOS transistors has a negligible impact on the CNTFET’s operation. The gate width in CNTFET is not the effective channel width of the transistor. This only depends on the CNT diameter and the number of tubes under the gate and does not affect the drive current. As in [38] only the CNT diameter has the strongest impact on the CNTFET performance while other process variations have only a small impact. Monte Carlo simulation by HSPICE has been performed to investigate the impact of the random variations on the delay and power of the CNTFET and CMOS SRAM cells at 0.9 V power supply and room temperature. Figure 23 shows the distribution of the write time of the CNTFET and CMOS 6T SRAM cells under geometric parameters with random changes. All simulation results are normalized to the SRAM’s write time under no process variation. Figure 23 shows that the write time of the proposed dual-diameter CNTFET 6T SRAM cell has much better tolerance to process variations compared to its CMOS counterpart. Figure 24 shows the distribution of the standby power consumption of the CNTFET and CMOS 6T SRAM cells. Likewise the previous cases, all simulated results are normalized to the SRAM cell standby power consumption under no process variation. Due to the significantly low standby power consumption and fewer parameters causing changes in power consumption, the CNTFET SRAM cell shows a significantly better tolerance to process variations.

As dimensional scaling of CMOS transistors is reaching their fundamental physical limits, various researches have been actively carried out to find an alternative way to continue to follow Moore’s law. Among these efforts, CNTFETS turned out to be the most promising candidate. To test the feasibility of the CNTFET technology, a different type of logic circuits including combinational and memory elements have been investigated. To maximize the benefits of the CNTFET technology, ternary logic circuits have been reviewed with test cases. In more detail, the CNTFET based combinational logic gates have been compared with the counter part of CMOS bulk CMOS technology in terms of power and delay and ternary logic gates performance have been assessed and compared with CMOS binary logic circuits.Since the memory component of the modern VLSI systems becomes more important, SRAM cell has been designed using CNTFET and its performance has been assessed in terms of write/read time, SNM. A new comprehensive metric for SRAM cells denoted as SPR was used in this paper; SPR is a composite and versatile performance measure in terms of stability, power,and delay.

In all of the attempts from combinational logic gate and ternary logic gate to SRAM memory cell, CNTFET based digital circuits show a significant improvements compared to the design of nanoscale CMOS counterparts in terms of power consumption and area. The proposed dual-diameter CNTFET SRAM cell has a better SPR under write operation than its CMOS counterpart cell. Moreover, simulation has shown that the proposed dualdiameter CNTFET based SRAM design has significant lower sensitivity to process, voltage, and temperature variations.

Based on the review and observation of the CNTFET based digital logic circuits, it is fair to say that CNTFET based integrated circuits design is a viable solution to replace the conventional bulk CMOS technology and it turns out to be an effective choice of future technology if manufacturability issues such as controllability of metallic/semiconducting property and metallic contacts are taken care of.