The relentless evolution of electronics, information technology (IT), and communications has been mainly enabled by continuous progress in silicon-based complementary metal-oxidesemiconductor (CMOS) technology. This continuous progress has been maintained mostly by its dimensional scaling, which results in exponential growth in both device density and performance. The reduction in cost-per-function has steadily been increasing the economic productivity with every new technology generation. In addition to its scalability, the unique device properties such as high input resistance, self isolation, zero static power dissipation, simple layout and process steps have made CMOS transistors as the main components of the current integrated circuits (ICs). Today CMOS ICs are everywhere and indispensible in our life, ranging from portable electronics to telecommunications and transportation [1].

However, as device scaling continues for the 21st century, it turns out that the historical growth, doubled circuit density and increased performance by about 40% every technology generation, followed by "Moore's Law," [2, 3] cannot be maintained only by the conventional scaling theory. Increasing leakage current does not allow further reduction of threshold voltage, which in turn impedes further supply voltage scaling for the historical speed improvement. Accordingly, generated higher electric fields inside of the transistor worsen device reliability and increase leakage currents. Moreover, the required high channel doping causes significant challenges such as mobility degradation, increased band-to-band tunneling (BTBT), gate-induced drain leakage (GIDL) and random dopants induced threshold voltage fluctuations [4].

Due to those ever increasing short channel effects (SCEs), there have been several strategies introduced for CMOS device to extend Moore's Law. A few examples of those are; increasing electrostatic control over the channel by means of the continuous equivalent oxide thickness (EOT) scaling with high-k/metal gate stack, multi-gate structures for higher drive current at the constant over-drive voltage, improving carrier mobility by adopting high mobility channel materials, and strain engineering and reducing parasitics.

In addition, various researches have been actively carried out in device domain to find an alternative device to continue to sustain Moore's Law. Among these efforts, various kinds of alternative memory and logic devices (beyond CMOS devices) have been proposed. These nanodevices take advantages of the quantum mechanical phenomena and ballistic transport characteristics under low supply voltage and consume low power. Furthermore, due to their extremely small sizes, those devices are expected to be used for ultra-high density integrated electronic components having billions of devices in a single chip. However, it also increases defects and variations both during manufacture and chip operations.

In the introductory part of this paper, after the CMOS technology scaling trend and "Small-Geometry Effects" are reviewed to understand what impedes further down-scaling of planar bulk metal-oxide-semiconductor field-effect transistors (MOSFETs), the current and tentative efforts to cope with the limiting factors are discussed. After the CMOS scaling issues are reviewed, present and promising nanotechnology devices such as siliconon- insulator (SOI) devices, Multi-gate FETs, Si nanowire/cabon nanotube FETs are investigates in terms of their advantages/ drawbacks, basic operation principles, current state of development, and challenges for commercialization along with other possible options. Finally, this paper will conclude with a discussion of the various challenges to be resolved for nanoelectronics to be a full-brown technology from device to system architecture level.

It is important to have a solid understanding of the phenomena that occurs in nanoscale MOSFETs since it not only provides useful interpretation of the anomalies that we might encounter in their SPICE simulations but also provides us the future possibilities and limitations of the device scaling. In this section, we will review these phenomena starting from a brief overview of scaling trend of silicon-based planar bulk MOSFETs and highlight the challenges to be solved. Current approaches to control these small-geometry effects such as increased leakage currents, threshold voltage variations, weakened gate controllability over the channel, and increased in S/D resistances will be discussed.

Since the first MOSFET was successfully demonstrated in 1960 [5], in order to keep up with the increasing demand for faster, smaller, and cheaper products, lots of efforts have been made to shrink the size of MOSFET switching devices in semiconductor industry. Without any significant fundamental changes, the basic structure of MOSFETs has been evolved to continue its successful geometric scaling. The fundamental principles to scale down devices have been guided by the ideal scaling principles formulated by Robert Dennard in 1974 [6], and it is based on a simple electrostatics; if the device dimensions (W, L, and t_ox) and voltages (V_DD and V_th) are scaled down by the factor of α with the increased doping concentration by α (>1), all electric fields in the scaled transistor will remain the same as it was in the original device, hence named "constant-field scaling." Historically, the geometric scaling factor of each new generation has been α=√2 so the number of transistors per unit area doubles every technology generation [2, 3]. To achieve higher circuit density and performance while maintaining device reliability and constant power dissipation per unit area, there have been considerable reductions in the device dimensions and supply and threshold voltages. Recently, however, as the supply voltage (V_DD) scaling approaches to 1 V, the conventional scaling has been deviated from the ideal constant-field scaling due to the difficulty of further lowering the threshold voltage (V_th). This fundamental problem stems from the nonscalabe characteristic of the thermal voltage (V_T = kT/q) which makes the relatively fixed sub-threshold swing (S) at the constant temperature [7-9]. This, in turn, makes the sub-threshold leakage current increase exponentially as the V_th reduces. Therefore, there exists a lowest possible value of V_th, which is determined by the application constraints related to power consumption and circuit functionality. In addition, with the knowledge of increased V_th variation in nanoscale MOSFETs, it is necessary to make an enough margin for V_th variation to ensure that V_th stays well away from the lowest possible value of V_th [10]. Furthermore, especially for high-performance (HP) logic technology, it is required to keep a certain level of V_DD-V_th, which determines the drive current and hence performance in a chip. It makes further down-scaling of the supply voltage difficult. Fig. 1 shows the difficulty on supply voltage scaling. Under fixed V_th, reducing V_DD trades off performance (speed) and leakage power. The power density trend between the active and standby power is shown in Fig. 2. These trends in technology scaling have made us enter a new era in achieving high performance under constrained power [8].

2.2.1 Channel

1) Sub-threshold leakage current: The Sub-threshold leakage current is the weak inversion conduction current, which is dominated by the diffusion current flowing between the drain and source when 'V_GS' < 'V_th'. It is considered as one of non-ideal characteristics of MOSFET as a switching device and contributes major portions of the standby leakage power dissipation. This weak inversion conduction current can be expressed based on the Eq. (1) [11],

where (특수문자) denotes the capacitance of the depletion region under the gate area, V_T is the thermal voltage which equals to kT/q, and n is the sub-threshold parameter and expressed as 1+C_dep/C_ox. Since, from Eq. (1), I_subth increases exponentially with both increasing V_GS and decreasing V_th, the partial derivative of log₁₀I_subth with respect to V_GS yields a constant slope called "sub-threshold slope (SS)" and equals to

This parameter shows how abruptly the transistor turns off with decreasing gate voltage. In order to turn off the transistor effectively, S must be designed to be as small as possible. Fig. 3 shows that S is always greater than 2.3 V_T (~60 mV/dec) at room temperature and shows how well the channel surface potential can be controlled by the gate contact. S can be made smaller (close to ~60 mV/dec) by using a thinner gate oxide thickness (resulting in larger C_ox) or a lower substrate doping concentration (resulting in the larger depletion width beneath the channel, hence reduced C_dep). In addition, under lower temperature operation, S can be reduced since S is a function of T. For MOS a transistor built in SOI technology, the sub-threshold swing is usually better than in bulk technology. In fact the sub-threshold swing of SOI devices can even reach the optimum value (2.3 V_T) depending on whether their bulk is fully depleted or partially depleted. This makes SOI a promising candidate for ultra lowpower CMOS applications though a lot of improvements to the current process technologies still have to be made until this new technique can be applied to commercial products on a large scale [11, 12].

2) Threshold voltage variation: Since the threshold voltage (V_th) variation is directly related to the device speed and subthreshold leakage current, it has to be minimized. It is generally explained in terms of 1) V_th roll-off (or falloff ) and 2) Drain induced barrier lowering (DIBL).

The transistors with a different channel length (L) in the same wafer, even in the same die, yield difference V_th. The threshold voltage reduction due to the reduced channel length represents V_th roll-off. Further V_th reduction caused by increasing drain voltage describes DIBL as shown in Fig. 4. Both phenomena stem from the lowered potential barrier between the drain and source due to the relatively increased charge-sharing effect between the channel depletion region and source/drain depletion regions comparing to long-channel device case. This charge-sharing effect makes a transistor require less gate voltage to deplete the substrate beneath the gate dielectric and makes V_th decrease [11- 13].

If the depletion region around the drain continues to extend to the source depletion region with the further increasing drain voltage and finally merges together before junction breakdown occurs, the drain current increases due to the existence of a parasitic current path located well below the gate. This phenomenon is known as punch-through and added up to the sub-threshold leakage current. In order to prevent the punch-through effect, one might think that an increase of the overall substrate doping level may be helpful to reduce D/S depletion regions. However, the higher doping also increases the sub-threshold swing (S) (as explained in section 2.2.1), BTBT current and GIDL current, and also it causes carrier mobility degradation. Therefore, it is not the best option to reduce the leakage current [4, 12, 14].

All these phenomena are collectively referred to as "shortchannel effects (SCEs)" and tend to increase standby leakage power dissipation. To mitigate SCEs, an advanced MOSFET, depicted in Fig. 5, uses the silicidation of S/D junctions and lightly doped drain/source (LDD) structure with pocket halo implant and super-steep retrograde body doping [12, 15-17].

Additionally, increasing random dopant variations (RDF) and line-edge roughness (LER), particularly non-rectangular gate can cause significant statistical V_th variation and in turn severely affect circuit stability as well as performance distribution [18- 20].

3) Carrier mobility degradation: Since the rate of the supply voltage scaling has been reduced while the geometric scaling keeps the same historical rate, the electric fields inside the MOSFETs keep increasing. The drift velocity of the carriers is proportional to the longitudinal electric field across the channel at low field (<10³ V/cm). After that point, however, the increasing rate of the carriers' velocity decreases with the increasing longitudinal field in Si at room temperature. Finally, the carriers reach their maximum velocity of v_sat~10⁷ cm/sec when the electric field exceeds ~3 × 10⁴ V/cm for electrons and ~10⁵ V/cm for holes (here the channel length (L) is assumed to be much greater than the average distance (l) between scattering events such as L>>10 nm.) This carrier mobility degradation is called "Velocity Saturation," and originates from various scattering mechanisms such as optical phonon scattering, phonon dispersion, phonon absorption as well as emission, and the energy band non-parabolicity [21, 22].

Another high electric field is developed between the gate and the channel due to the aggressive gate oxide thickness scaling with relatively constant supply voltage, which limits the charge carriers to a narrower region below the oxide-silicon interface, leading to more carrier scattering and hence lower mobility. Furthermore, the increased body doping by means of suppressing SCEs degrades the carrier mobility [21].

4) Hot carrier effects (HCEs): The high electric fields in a device also cause reliability problems such as threshold voltage shifts and trans-conductance degradation due to "Hot Carrier Effects (HCEs)." As the average velocity of carriers in the channel saturates by the increased scattering rate at the high electric fields, the carriers can attain high kinetic energy. Once those hot carriers obtain sufficient energy to overcome barriers, they might migrate into the unwanted area such as the gate dielectric, gate, or substrate of a transistor. Especially, the highly accelerated hot carriers near the drain region can generate new electron-hole pairs by collision with the silicon atoms, which is called "impact ionization." Impact ionization can cause significant increase in substrate current or carrier injection into the gate dielectric, which causes charges to get trapped in the gate oxide. This causes threshold voltage shifts and therefore the device becomes unstable and even can fail [19, 21].

The lightly LDD MOSFETs, shown in Fig. 5, have been widely used to reduce the maximum longitudinal electric field in the channel by means of the additional voltage drop across the higher resistive LDD region. As a result, the LDD technique increases hot carrier immunity in a device, but also degrades the device performance [15, 21].

5) Direct source to drain tunneling: The ultimate physical scaling limit of MOSFETs is direct source-to-drain tunneling. If the barrier width (transistor channel length) between source and drain becomes small enough for electrons to tunnel through the barrier without any additional gate bias, MOSFETs no longer can be used as a switch. When we consider only over-barrier transition of electrons but the direct tunneling, from the well-known Shannon-von Neumann-Landauer (SNL) expression, the minimum energy barrier to separate two different states of electrons is E_SNL = k_BT(ln2) = 0.017 eV at room temperature (T = 300 K), where k_B is the Boltzmann constant and T is the temperature. Therefore, the smallest energy required to process a bit is E_bit > E_SNL = k_BT(ln2) = 0.017 eV. Also, according to quantum mechanics the minimum channel length (barrier width) able to resist E_bit, not to allow tunneling, is about 5 nm. In order to achieve a smaller channel length, it is necessary to increase the Ebit. However this, in turn, tradeoffs with the growth of total power dissipation in a chip. Therefore, enhanced cooling techniques become the critical issues to achieve this goal [23, 24].

2.2.2 Gate

One of the key innovation enablers for 45 nm process technology and beyond is the high-k/metal gate transistor, which is regarded as one of the biggest developments in transistor design in 40 years [25]. High-k/metal gate have enabled the continuous EOT scaling. In this section, the motivation for using high-k/ metal gate stack in advanced CMOS devices is discussed.

1) Direct tunneling gate leakage current: With the continuous device scaling, the gate oxide thickness has been accordingly reduced to maintain the gate controllability over the channel. However, as the gate oxide thickness scales below 2 nm, the direct tunneling (DT) gate leakage increases exponentially due to quantum mechanical tunneling. The DT gate leakage current can not only increase standby power dissipation but also limit the proper device operation [26]. These serious problems can be solved by replacing SiO₂ with higher permittivity (high-k) gate dielectrics, which allows a physically thicker dielectric layer to have an EOT [27]. Recently, high-k dielectric based on Hafnium and dual metal gate has been introduced to increase transistor performance while also reducing gate leakage as gate dielectric thickness actually increased while also the gate capacitance increased [25].

2) Gate depletion: Polycrystalline silicon (poly-Si) has been widely used as the gate electrode material of MOSFETs since it replaced aluminum on account of its superior thermal stability to higher processing temperature. In addition, the use of poly-Si as gate electrode has reduced the overall number of processing steps by means of self-aligned processing, where the gate itself is used as a hard mask during ion implantation for the source and drain junction formation. This technique allows tighter overlap between gate and source/drain regions and results in lower parasitic capacitance. Lastly, by controlling its doping concentration, the work function of the poly-Si can be easily tuned [28].

However, even heavily doped poly-Si gate electrode has a certain resistance which contributes to a considerable RC time delay. Furthermore, when the doping concentration of the poly- Si is not sufficient, at high gate bias during inversion, a region in the poly-Si gate electrode adjacent to the poly-Si/SiO₂ interface becomes depleted with carriers, which is called "Poly-depletion Effect." This results in increased EOT and hence significant decrease in the drive capability of transistor. To improve gate depletion, the number of active dopants in the gate electrode can be increased, but this solution is limited as current doping concentrations are already nearing the equilibrium solid solubility in silicon [27, 28].

For these reasons poly-Si is not suitable for the future gate electrode and new materials are required. Fortunately, metal gate electrode with a suitable work function (WF) shows many advantages such as lower gate sheet resistance and no boron penetration and poly depletion effect. However, the selection of metal gate substitutes for poly-Si, which are compatible with the new high-k gate dielectrics, is not as advanced [29].

2.2.3 Drain/source

1) Parasitic resistance (suppress on-current): As the device gets smaller, the influence of parasitic resistance on on-current increases significantly. Therefore, proper control of parasitic resistance in a MOSFET becomes more important to achieve further performance improvement. The total parasitic resistance, which accounts for the voltage drop between channel and S/D contacts, can be divided into the four components such as overlap resistance, extension resistance, deep resistance, and silicide-diffusion contact resistance [30]. Shallower S/D junction depths are desired to suppress SCEs effectively; however, since the shallower junction also increases the sheet resistance, the S/D doping must be increased accordingly to keep the sheet resistance constant. However, as the maximum solid solubility of dopants is limited to ~10²⁰ cm^-3 on the doping density, the series resistance increases with further reduction in junction depth. In addition, the ultra-shallow junctions are difficult to form and also cause significant increase in BTBT leakage current [31]. Furthermore, since the silicide-to-junction contact resistance accounts for nearly half of the total parasitic resistance in state-of-the-art MOSFETs, it is necessary to reduce the contact resistivity to meet the scaling requirement. Contact resistivity can be lowered by increasing the active dopant concentration at the silicide-tojunction interface or reducing the Schottky barrier height in contact region [32].

2) Parasitic capacitance: In digital applications, lower capacitance, along with higher drive current, is the main factor for high performance CMOS circuit design, because the conventional CMOS inverter delay model is given by C_GV_DD/I_D, where C_G is gate capacitance, V_DD is supply voltage, and I_D is drain on-current. Thus, with geometry scaling, the performance improvement has been achieved because the gate capacitance consisting of both intrinsic gate capacitance (C_int = C_GC + 2C_OV) and parasitic capacitance (C_para ~ C_fringe + C_gco) decreases in proportion to the gate length reduction in micro MOSFET, where C_GC is gate-tochannel capacitance, C_OV is drain/source-to-gate electrode overlap capacitance, C_fringe is inner/outer fringing capacitance, and C_gco is gate-to-contact capacitance. However, as MOSFET enters into nano regime, gate capacitance does not decrease in proportion to the gate length reduction due to relatively increased parasitic capacitance. Therefore, in order to sustain performance improvement from scaling, parasitic capacitance reduction technique is required [33].

2.2.4 Substrate (bulk)

Substrate leakage current consists of impact ionization current, reverse-biased junction leakage current (mostly BTBT leakage current), and GIDL current.

1) Reverse-biased junction leakage current (reverse-biased band-to-band tunneling current): Reverse-biased junction leakage current (I_REV) is the current flowing between the source/drain (S/D) and the substrate through the parasitic reverse-biased pnjunction diode in the off-state MOSFET. I_REV mainly consists of the diffusion and drift of minority carriers near the depletion region edge and the generation of electron-hole pairs in the depletion region of the reverse-biased pn-junction. The amount of I_REV depends on the junction area and doping concentration. If both S/D and substrate regions are heavily doped, BTBT dominates the I_REV since the electric field across the junction depletion region increases. If the high electric field (>10⁶ V/cm), so that the voltage drop across the junction is bigger than the band gap of silicon, is formed across the reverse-biased junctions of the source/drain (S/D) regions, especially with increasing S/D voltage or reverse body bias, significant amount of BTBT current flows through the S/D to substrate junctions. In nanometer devices, higher channel and S/D doping with shallow junction depths are required to minimize SCEs, there is significant increase in BTBT current [34].

Recently high-mobility channel materials, such as Ge, strained-Ge (s-Ge), s-SiGe, and III-V materials (GaAs, InAs, InSb, and InGaAs), are actively being researched as candidates for future channel materials of highly scaled MOSFETs. However, since most of high-mobility materials have lower band gaps than Si, BTBT leakage currents increase significantly. Therefore, various device structures to minimize BTBT currents are being developed [35]. The various leakage mechanisms in a MOSFET are illustrated in Fig. 6.

2) GIDL current (Surface BTBT current): GIDL current, also called surface BTBT current, has become one of the major offstate leakage current components in state-of-the-art MOSFETs. When the drain of n-MOSFET is biased at the supply voltage (V_DD) and the gate is biased at either zero or negative voltage, a depletion region is formed under the gate and drain overlap region. In the same way as the BTBT current, if the high electric field is formed in the narrower depletion region as a result of the reverse-bias between channel and drain, a significant amount of surface BTBT current flows through drain to substrate junctions due to twisting of bandgaps [36, 37]. With higher supply voltage, thinner oxide thickness, LDD, reverse body bias (RBB) technique, and high mobility channel materials having smaller bandgaps enhance the GIDL current.

2.3 Summary

As the device scaling is approaching its physical size limitations, the technology cycle is getting slow down due to increasing power consumption, process variation, and fabrication cost. To continue the historical growth for the next decade, various studies have been conducted to overcome ever increasing challenges. As explained in section 2.1, nowadays device scaling tradeoffs between performance and power consumption, therefore technological innovations which can achieve high performance through very low power are required. These efforts have made conventional MOSFETs evolve in various ways with new materials, new structures, and so on. In the next section, the evolution of MOSFET structures is reviewed.

The conventional device scaling trend, which is mostly based on reducing its physical size, is no longer valid for the future technology generations. Therefore, several strategies have been introduced to extend Moore's Law, such as increasing electrostatic control over the channel by means of the continued EOT scaling with high-k/metal gate stack and multi gate structures for higher drive current at constant over- drive voltage (V_DD-V_th), improving mobility of carriers by adopting high mobility channel materials and strain engineering, reducing parasitics, and so on [38].

The advantages of SOI technology come from its buried oxide (BOX) layer (a cross-section of a SOI device is shown in Fig. 7). With the reduction of the parasitic capacitances, mostly as a result of the reduced drain/source junction capacitances, SOI devices yield improved switching speed and reduced power consumption. The operating speed is also improved since the isolated channel from substrate bias prevents the increase in a threshold voltage of stacked SOI transistors. In addition, the perfect lateral and vertical isolation from substrate provides latchup and inter-device leakage free CMOS technology, reduction in various interferences, and better soft error immunity. Moreover, SOI technology offers tighter transistor packing density and simplified processing [39].

SOI transistors are classified into two types; "partially depleted (PD) SOI," if the silicon film (typically 100 nm or more) on the BOX layer is thicker than the depletion region depth beneath the gate oxide, and "fully depleted (FD) SOI," if the body (silicon film) thickness is thin enough (typically 50 nm or less) or the doping concentration of the body is low enough to be fully depleted. FD SOI transistors have superior advantages over PD SOI transistors in terms of extremely low sub-threshold swing (<65 mV/decade), no floating-body effects, and low threshold voltage variation with temperature (2-3 times less). However, since FD SOI transistors are even more sensitive to process variation such as the silicon film layer variation resulting in threshold voltage fluctuation, PD SOI devices were commercially introduced first. With careful device design and advanced process techniques, fully depleted ultrathin-body SOI (FD UTB SOI) devices are considered as one of the best scaling options. Undoped or very lightly doped UTB devices minimize impurity scattering and reduce threshold voltage variation resulting from random dopant fluctuation [40].

Another important merit of SOI technology is that it provides the cornerstone for new device structures such as multi gate field-effect transistors (MuGFETs), which includes more than one gate into a single device. The double-gate (DG) FET shown in Fig. 8(b) is the first step for those multi gate devices. Since the transverse electric field induced by V_DS is shared by both top and bottom channels, it mitigates SCEs [38, 41]. However, since the gate-channel-gate stacked structure is not suitable for Si-planar technology to fabricate, the complex fabrication processes are required to form DG FETs. These problems are considerably eased with a self-aligned FinFET (Fig. 8(c)) [42]. In addition to DG FET and FinFET, tri-gate, gate-all-around (GAA) (or surround-gate), and nanowire FET structures (Figs. 8(b)-(f )) show the better drive current at fixed V_DD in order. Especially, a thin nanowire channel FET, shown in Fig. 8(f ), provides the most effective electrostatic characteristics via the gate bias.

On the other hand there is a significant drawback in SOI technology. Since the BOX, which has approximately 100 times lower thermal conductivity than that of silicon, prevents thermal conduction path from SOI transistors to the substrate, SOI transistors are easily affected by the thermal heating generated in the channel, which is called "Self-Heating Effects." Consequently, the self-heating degrades the mobility of carriers and causes the threshold voltage shift. These effects get worse with FD structures because they use thinner silicon films [43].

Mobility loss resulted from higher channel doping and scaled gate dielectrics should be compensated to meet the performance targets of the future technologies. In the parallel with SOI technology, there has been more straight forward and cost effective way to improve device performance and scalability. That is mobility-enhancement technology. Both the high mobility channel materials (such as Ge and GaAs) and the strained channel by means of stress offer mobility enhancement. Various CMOS fabrication processes can be used to induce appropriate strain to the channel region of the MOSFETs. Strain engineering can be largely divided into two: local strain and global strain. Local strain exploits the process steps such as shallow trench isolation (STI), silicidation at the source/drain (S/D) region, and nitride CESL (Contact Etch Stop Liners). The local strain techniques were first used because they were more promising for manufacturing. However, since they have strong device geometry dependence, it makes their scaling behavior less predictable. The most innovative way on strained-Si was focused on biaxial global strain generated by depositing a thin layer of silicon on a relaxed SiGe virtual substrate. This results in enhanced carrier transport in the strained Si layer, and mobility enhancements of 110% for electrons and 45% for holes. A cross-section of transistors with strained Si-channel fabricated by means of both the global and local strains is shown in Fig. 9 [44-46].

Appropriately applied strain to the MOSFET channel can significantly improve the device performance by means of modifying energy bands and increasing mobility of carriers in silicon. Strain is being widely used in HP logic technologies. SiGe in the PMOS S/D regions, stress memorization technique (SMT) for the NMOS, and a nitride stress-capping layer for both devices have been commonly employed in state-of-the-art MOSFETs since its introduction at the 90nm node. Strain is expected to continue CMOS technology scaling for the time being [47].

As dimensional scaling of CMOS transistors is reaching their fundamental physical limits, various researches have been actively carried out to find an alternative way to continue to follow Moore's law. Among these efforts, various kinds of alternative memory and logic devices, so called "Beyond CMOS Devices," have been proposed. These nanodevices take advantage of the quantum mechanical phenomena and ballistic transport characteristics under lower supply voltage and hence low power consumption. Those devices are expected to be used for ultra high density integrated electronic computers due to their extremely small size. In the following sections, the general overview will be discussed for the promising emerging logic nanodevices such as nanowire (NW) transistors, carbon nanotube field-effect transistors (CNTFETs), graphene nanoribbon (GNR) transistors, single electron transistors (SETs), and quantum-dot cellular automata (QCA) in terms of their basic operation principles, current state of development, and challenges for commercialization.

There are a number of nanoelectronic devices that can possibly supplement or replace current CMOS devices. These include nanowire or carbon nanotube transistors, graphene FETs, single electron transistors, and spin transistors. These devices offer sizes of a few nanometers and can be self-assembled.

Nanowire field-effect transistors (NWFETs), gate-all-around or surround gate FETs with a thin nanowire channel, have drawn much attention and have been considered as promising candidates for continuous CMOS scaling since their nonplanar geometry provides superior electrostatic control of the channel than the conventional planar structures. The increasing attention in nanowire research stems from several key factors: their highyield reproducible electronic properties [48-50], cost-effective "bottom-up" fabrication which circumvents some fabrication challenges, higher carrier mobility by means of the reduction of scattering resulting from the crystalline structure, smooth surfaces and the ability to produce radial and axial nanowire heterostructures [51, 52], better scalability resulting from the fact that diameter of nanowires can be controlled down to well below 10 nm [53, 54].

However, due to their smaller nanowire diameters, the inversion charge changes from surface inversion to bulk inversion due to quantum confinement. Thus, variations in nanowire dimensions due to fabrication imperfections can lead to perturbations in the carrier potential and scattering that degrade the charge transport characteristics. Also, variations in nanowire diameters may lead to a variation in FET threshold voltage. Reducing variability is therefore a key challenge in making nanowire FETs a viable technology. Furthermore, quantum confinement effects make modeling of nanowire transistors a complex problem. While there are many studies in the literature on the modeling of nanowire transistors based on nonequilibrium Green function or Monte Carlo approaches, the physics related to the operation of nanowire transistors needs to be well articulated so that simple compact models, including ballistic transport and realistic subband parameters, can be developed for circuit design using SPICE-like simulators [55].

Since they were discovered in 1991 [56], due to their unique material properties [57], carbon nanotubes (CNTs) have received worldwide attention from many different fields of scientists and engineers.

CNTs are graphene, which is a two-dimensional honeycomb lattice of carbon atoms, sheets rolled up into cylinders. They show either metallic or semiconducting properties depending on the direction how CNT are rolled up (chirality). Since the bandgap of semiconducting CNTs is inversely proportional to their diameters, threshold voltage can be easily controlled [58-60].

With their superior material properties, such as large current carrying capacity, the excellent mechanical and thermal stability, and high thermal conductivity, the metallic nanotubes are attractive as future interconnects [61]. Along with these properties, the semiconducting nanotubes also show great advantages as a channel material of high-performance (HP) FETs. It is easier for CNTFETs to incorporate high-k dielectrics due to the absence of dangling bonds. Also, since both NMOS and PMOS transistors show almost identical I-V characteristics, it becomes a significant advantage for CMOS circuit design. Furthermore, they are very attractive to Si-based semiconductor industry for the following reasons: 1) CNTFETs show considerable improvement in device performance metrics such as low power and high speed 2) their operating principles and devices structure are similar to Si-based CMOS transistors; therefore, the CMOS design infrastructure could be reused [62].

Even though CNT-based electronics presents great promise, there are several difficult challenges to be solved. No existing processes for synthesis or growth of nanotubes can produce tubes with identical diameters and chiralities. The starting material will have to be purified if far more selective growth processes cannot be developed. Many progresses are being reported in purification. However, there is still a big gap between these promising early results and the extremely tight control of placement that would be needed. Furthermore, an even tighter gate control through ultrathin high-k gate dielectrics and extremely abrupt doping profiles are required for the device fabrication [63].

Graphene, a single atomic layer of carbon atoms arranged into a two-dimensional (2D) hexagonal lattice, or simply thought as an unrolled CNT, shows great potential for nanoelectronic devices since its discovery in 2004 [64]. It shares many of the advantages of metallic CNTs such as the high carrier mobility for ballistic transport, high carrier velocity for fast switching, excellent thermal conductivity, and etc. The potential to produce wafer-scale graphene films with full planar processing for devices promises high integration potential with conventional CMOS fabrication processes, presenting a significant advantage over CNTs [65].

Two-dimensional graphene has a zero band-gap (E_G) semimetal characteristic. However, by patterning graphene into a few nanometer wide GNR, a band-gap can be induced [66]. Similar to the CNT cases, GNRs have energy band-gap which is inversely proportional to their width, and width confinement down to the sub-10 nm scale is essential to open a band-gap that is sufficient for room temperature transistor operation. Unlike CNTs, which are mixtures of metallic and semiconducting materials, recent samples of chemically derived sub-10 nm GNRs have shown allsemiconducting behavior [67]. GNRs, under the assumption that the edges of ribbons are passivated by hydrogen atoms, have two main types of armchair-edge and zigzag-edge GNRs (AGNRs and ZGNRs). ZGNRs are predicted to be metallic by a simple tightbinding model, but a band-gap exists in more advanced and spin-unrestricted simulations [68]. For digital circuit applications, the focus has been on using AGNRs as the channel material. AGNRs have an electronic structure that is closely related to that of zigzag CNTs. The band-gap in AGNRs originates from quantum confinement, and edge effects play a critical role [68, 69].

Due to the atomically thin and nanometer-wide geometries of GNRs, variability and defects are projected to have a larger impact on GNRFET circuit performance and reliability in comparison to the conventional silicon devices. Variability, for example, can arise from the difficulty of control of the GNR width, edge roughness, or oxide thickness during fabrication. Defects may occur during fabrication due to a charge impurity in the gate insulator or a lattice vacancy, and result in a large performance variation or a nonfunctional device. Not only must each of the variability and defect mechanisms be identified and studied, the models developed for GNRs and GNRFETs must be capable of predicting their effects in isolation as well as together in a systematic manner [69].

Although the GNR material promises ultra-small, fast, and low-energy FETs, two key effects of variability and defects - leakage and low noise margins - are significant. For example, the variation of the channel width by a couple of angstrom changes the leakage current by orders of magnitude, and a single Coulomb charge impurity can lower the FET on-current by about 30%. Dense memories, which are the biggest prospect for graphene- based devices, are particularly susceptible to variations and defects with near-zero noise margins and an increase in leakage power of over 5 X. This assessment of the effects of variability, defects, and parasitics indicate their important role on circuit performance. These effects must be carefully considered in the performance assessment and design optimization for future graphene-based electronics technology [70].

4.4 Single-electron transistors (SETs)

Due to their small size and low-power dissipation at good speed, SETs are very attractive devices for future large-scale integration. The basic structure of SET consists of three-terminals such as drain, gate, source, and the second gate is an optional. A schematic of SET, as shown in Fig. 10, is analogous to that of conventional MOSFETs. However, SET has a tiny conductive island coupled to a gate electrode with gate capacitance C_g. Source and drain electrodes are connected to the island through a tunnel barrier (junction). The tunnel barrier, which controls the motion of every single electron, consists of two conductors separated by thin layer and it is modeled as tunneling resistances R_{D, S} and junction capacitances C_{D, S}. The increased gate bias attracts electrons to the island only through either drain or source tunnel barrier, and the number of electrons in the island only has a fixed integer. Therefore, the increased gate bias makes electrons flow one by one when a small voltage is applied between the source and drain electrodes by means of the "Coulomb blockade" phenomenon [71-73].

New applications and architectures that exploit the unique functionality of room temperature operating SET circuits have been developed, especially by monolithic integration of SETs with FET circuits to complement the conventional Si CMOS performance. Representative examples include SET/CMOS hybrid multi-value logic circuits [74], multiband filtering circuits [75], analog pattern matching circuits (discussed more fully in the next section) [76], associative recognition tasks [77], and others [78], in which characteristic Coulomb blockade oscillations of SETs are typically utilized to reduce the number of devices. Note that certain aspects of the circuit performance, especially the room temperature operation [76, 79], already exceed the theoretical evaluation of the logic gate parameters for 2 nm SETs. These devices have a theoretically estimated maximum operation temperature T~20 K, integration density n~10¹¹ cm^-2, and speed of the order of 1 GHz [80]. However, large threshold voltage variation continues to impede the realization of large scale SET circuits, making it difficult for SETs to compete directly with CMOS devices used to implement Boolean logic operations. Engineering breakthroughs are needed to eliminate the size and background charge fluctuations in order to suppress the threshold voltage variations.

The majority of the SET circuits demonstrated to date employ so called "voltage state logic," where a bit is represented by the voltage of capacitor charged by many electrons. The problem of the low fan-out for this scheme can be overcome by reducing the capacitance and/or by combining with conventional FET circuits. Truly single-electron approaches, representing a bit by a single electron ("bit state logic") [81] and the use of a single electron as a source of random number generations [82], have been limited to laboratory demonstrations. The problem of the limited fan-out, which is caused by using only a single electron in the truly single-electron devices, may be solved by innovative circuit designs such as the binary-decision-diagram [83].

As the number of transistors placed onto a single chip increases, the heat generated during a switching cycle can no longer be removed and this may result in considerable limitation of the speed of operation. There is a new paradigm which takes advantage of the reduction of the feature size. One nanostructure paradigm, proposed by Lent et al. [84-86], is QCA, which exploits arrays of coupled quantum dots to implement Boolean logic functions. The advantage of QCA lies in the extremely high packing densities possible due to the small size of the dots, the simplified interconnection, and the extremely low power-delay product [87].

A schematic diagram of a four-dot QCA cell is shown in Fig. 11. This is the simplest non-clocked QCA cell. The cell consists of four quantum dots positioned at the comers of a square. The cell contains two extra mobile electrons, which are allowed to tunnel between neighboring sites of the cell, but not out of the cell. If the tunnel barriers between cells are sufficiently high, the electrons will be well localized on individual dots. The Coulomb repulsion between the electrons makes them occupy antipodal sites in the square as shown. For an isolated cell, there are two energetically equivalent arrangements, polarizations, of the extra electrons that we can denote as binary 1 and binary 0. The two polarization states of the cell will not be energetically equivalent if other cells are nearby, because the Coulomb interaction with other cells breaks the degeneracy [87].

A QCA wire is shown in Fig. 12(a). The left-most cell is fixed with polarization representing the input. The difference between input and outputs cells in QCA arrays is simply that inputs are fixed and outputs are free to change. The ground state configuration of the remaining free cells is the one with each cell polarized in the same way as the input cell. We can consider this transmission of the input signal from one end to the other. Cells that are positioned diagonally from each other tend to anti-align. This behavior is employed to construct an inverter as shown in Fig. 12(b). Fig. 12(c) shows the fundamental QCA logical device, a three-input majority gate, from which more complex circuits can be built. The central cell, labeled the device cell, has three fixed inputs labeled A, B, and C. The device cell has its lowest energy state if it assumes the polarization of the majority of the three input cells. It is possible to "reduce" a majority logic gate by fixing one of its three inputs in the 1 or 0 state. In this way, a reduced majority logic gate can also serve as a programmable AND/OR gate. Combined with the inverter shown above, this AND/OR functionality ensures that QCA devices provide logical completeness [87].

For practical QCA circuits, clocked control is necessary. In clocked circuits, the system is switched smoothly between the ground state corresponding to the old inputs and the state corresponding to the new inputs. Clocking allows cells to be locked in a particular state, performing as a latch. Thus general purpose computing is possible, and in particular, latches make it possible to implement pipelined architectures as required in all highperformance systems [88].

A severe problem of QCA arises from the fact that QCA are single-electron devices and they are very sensitive to the background charge. Today, no viable solutions to the background charge immune single-electron systems are known. Another serious drawback of QCA devices is that room-temperature operation is not achievable with solid-state QCA systems [79].

While nanoelectronics presents the opportunity to incorporate billions of devices into a single chip, it also increases defects and variations both during manufacture and chip operations. In this chapter, technical challenges are summarized for nanoelectronics technology ranging from device to system architecture level.

Due to their extremely small size (tens of nanometers and below), quantum-mechanical effects such as ballistic transport, tunneling effects and quantum interference start to predominate in nanodevice operation. Therefore, good understanding of quantum-mechanical phenomena is required to exploit the properties of nanodevices.

Emerging Research Device (ERD) Working Group evaluated nanodevices in terms of nine relevance criteria; scalability, performance, energy efficiency, on/off ratio for memory devices, gain for logic devices, operational reliability, operation temperature, CMOS technology compatibility, and CMOS architectural compatibility. For logic applications, since the number of transistors in a chip is limited not by their size but by the maximum allowable power dissipation (~100 W/cm²), 1D structure devices such as NW transistors and CNTFETs are promising because they show higher I_ON/I_OFF ratio rate at lower supply voltage. In spite of their higher risk, channel replacement materials also have potential. While both of those charge-based channel replacement logic technologies show better device characteristics than other devices using computational state variables, state variable devices are expected to give us a solution for limitations of chargebased technology in long-term future. Due to their lacks of reliability, it is not likely for revolutionary nanoelectronic devices to replace CMOS technology entirely without compulsory needs for those devices. However, if used to complement ultimately scaled CMOS, they might present more possible ways to extend the functionality or reduce the power dissipation with their unique properties [89].

Suitable interconnect technology must be developed based on new device concepts. In order to connect extremely small devices, interconnects are required to be less than 10 nm in diameter. As the diameters of metallic interconnect wires scale down to the mean free path of electrons, both the surface scattering from the boundaries of ultra-narrow conductors and the grain boundary scattering would impede electronic conduction in the wires [90]. As a result, the circuit will be slower and it is not possible to achieve performance improvement from scaling. Furthermore, electromigration resulting from movement of lots of electrons and electron scattering makes another serious problem. Therefore, various potential interconnect technologies ranging from nanowires to carbon nanotubes and quantum wire have been extensively researched in order to satisfy the requirements such as low resistivity, large current carrying capacity, easy of fabrication, and isolation with low-k dielectric materials for ultra-high density applications [91].

Nanoarchitecture can be defined as the organization of basic computational structures composed of nanodevices assembled into a system that computes something useful. The design trends of nanoelectronics also can be summarized as increased emphasis on parallelism, strict constraints on localized interconnection, regularity in nanofabrics, and repair of faulty circuits' offline and possibly online. Particularly, the high unreliability of nanodevices is the most critical problem in constructing nanoelectronic systems. The defect prone fabrication process, especially from bottom-up self-assembly process, increases manufacturing defects. At the same time, the high occurrence of transient faults and variations results in higher dynamic fault occurrences as well. Therefore, following issues are needed to be investigated and solved:

(1) How to use huge numbers of nanodevices in an effective way, (2) How to deal with the offline and online errors, (3) How to ensure system reliability without performance degradation, and (4) How to maintain power dissipation in tolerable level [92]?

Even after the four fundamental architectural questions are answered, a few fundamental efforts should be made in order to exploit benefits of nanotechnology and minimize its drawbacks in architecture level. The efforts include mapping more algorithms into parallel forms, finding alternative computation and information representation models, and designing fault tolerant, reconfigurable, and power efficient systems [93].

To design circuit, first of all, we must be able to implement all necessary primitive logic functions and latches out of nanoelectronic devices. Since most of the bottom-up fabrication techniques are only feasible for non-restorable two-terminal devices as of today, one of the key design challenges is to provide signal restoration.

Besides it is necessary to bridge the dimension gap between the nanometer-scale pitch devices and the lithographic-scale devices without nullifying the benefits from nanoelectronic systems in order to provide an interface between the nanodevice/ nanowire and CMOS sub-systems.

Moreover, variability and reliability problem are expected to be the major concern in nanoelectronic circuit design during manufacture and chip operations in the same way as the conventional top-down CMOS technology has encountered. Furthermore, small signal levels cause lower signal-to-noise margins due to reduced supply voltage. Because these problems are even worsened with increasing thermal fluctuations and crosstalks, nanoelectronic devices will be much more unreliable. Due their molecular sizes, there will be always a non-trivial probability that individual contacts may be inadequate or devices are missing. Along with the doping and topology variations, this may show up as either variations in device parameters or even a complete lack of connection at some crosspoints. In addition to manufacturing defects, nanodevices may be susceptible to persistent changes over their operational lifetime due to ionizing-particle strikes, aging, movement of individual atoms, and temperature-induced variations. Furthermore, with the state stored in small numbers of electrons, ionizing particle strikes and statistical switching effects can induce a high rate of soft errors.

Therefore, new novel fault and defect tolerance circuit design technique and methodologies have to be developed for nanoelectronic low-power, high-speed and high-density systems to make the circuit reliable out of the unreliable components (devices and wires). These can be achieved with designing circuit with very regular structures rather than arbitrary geometries and [93, 94].

The primary purpose of computer-aid design (CAD) tools is to offer an effective means for designing and fabricating electronic circuits in various ways. It comprises modeling of process steps, behavior of the electronic devices and physical systems on computers, providing the analysis of design variants, changing the expression of designs in a form suitable for manufacturing, and so on. They also can execute many functions, including many forms of verification (geometrical and electrical design rule checking, several types of simulation) and various aspects of design synthesis (generation of masks from layout, automatic placement and routing, logic synthesis and optimization) [95-97].

As the designs increase in size and complexity, the importance of CAD tools are being enhanced. Since nanoelectronics uses a higher level of device integration than their CMOS counterparts, it will be required to revise or reinvent many existing synthesis, physical design, and verification methodologies and techniques to handle complex nanoscale designs. Due to the huge number of nanodevices in integrated circuits, it is necessary to raise the level of design entry and abstraction from register-transfer level to the architecture and system level in order to manage design complexity and increase design productivity with increasing defects and fault rates. Therefore, new design flows and tools are needed to optimize nanoelectronic circuits for better performance and yield. The most urgent step is to develop suitable tool sets that can address the nanofabrication processes and unique features of nanotechnology devices and fabrics. The next required step for circuit integration is to develop design tool sets that can optimize the circuits having error resilience with the aid of statistical design techniques. Those tools should be able to analyze and quantify the key sources of nanodevice and nanowire parameter variations and defects [93, 94].

One of the grand challenges for nanoelectronics is to establish a new manufacturing paradigm which enables the continuation of the cost-per-function reduction well down to several nanometers. Conventional lithography technique has been a main enabler for large-scale CMOS integration. However, this increases process and mask complexity as the technology generation advances below 100 nm node, significantly increasing manufacturing cost. Therefore, a nanofabrication technique which can control and produce billions of nanodevices in a quick, reliable and cost-effective way is a prerequisite to nanaoelectronics manufacturing.

Largely, there are two different fabrication methods for nanoelectronic circuits. The top-down fabrication refers to the technique employing many steps of sophisticated lithographic and etching techniques in order to pattern a substrate. On the other hand, in the bottom-up approach, individual devices and wires are manufactured first from nanomaterials, and then assembled into a circuit. This bottom-up technique includes gasphase methods such as chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), liquid phase methods, and etc. Although the top-down approach is dominant at present time, it is expected that bottom-up approach will play an important role in near future since many of those methods are both cost-effective and offer high throughput. While bottom-up self-assembly presents some advantages, the drawback of this is the difficulty on generating arbitrary patterns which can be formed using photolithography. Furthermore, due to increased defect densities, self-assembled circuits and architectures will have to be designed for defect tolerance [98].

As dimensional scaling of CMOS transistors is reaching its fundamental limits, various researches have been actively carried out to find an alternative way to continue to follow Moore's law. Among these efforts, various kinds of alternative memory and logic devices, so called "beyond CMOS" devices, have been proposed. These nanodevices take advantage of the quantum mechanical phenomena and ballistic transport characteristics under lower supply voltage and hence low power consumption. Moreover, due to their extremely small size, those devices are expected to be used for ultra-density integrated electronic computers. While nanoelectronics presents the opportunity to incorporate billions of devices into a single system, it also increases defects and variations both during manufacturing and chip operations. Therefore, an additional constraint, 'reliability,' has to be added to the conventional low-power, high-speed and high-density design consideration. Due to this additional constraint, it is necessary to develop a new knowledge and reliability paradigm for nanoelectronics in order to enable industries to predict, optimize and design upfront reliability and performance of nanoelectronics. The new paradigm should be in a multi dimensional space covering devices, interconnects, architecture, circuit design, CAD, and fabrication issues.