General SPICE Modeling Procedure for Double-Gate Tunnel Field-Effect Transistors

  • cc icon
  • ABSTRACT

    Currently there is a lack of literature on SPICE-level models of double-gate (DG) tunnel field-effect transistors (TFETs). A DG TFET compact model is presented in this work that is used to develop a SPICE model for DG TFETs implemented with Verilog-A language. The compact modeling approach presented in this work integrates several issues in previously published compact models including ambiguity about the use of tunneling parameters Ak and Bk, and the use of a universal equation for calculating the surface potential of DG TFETs in all regimes of operation to deliver a general SPICE modeling procedure for DG TFETs. The SPICE model of DG TFET captures the drain current-gate voltage (Ids-Vgs) characteristics of DG TFET reasonably well and offers a definite computational advantage over TCAD. The general SPICE modeling procedure presented here could be used to develop SPICE models for any combination of structural parameters of DG TFETs.


  • KEYWORD

    Compact model , Drain current , Inverter , Potential profile , TFET , Verilog

  • 1. ITRS report [Online] google
  • 2. Universal TFET model [Online] google
  • 3. III-V Tunnel FET Model [Online] google
  • 4. Biswas A., De Michielis L., Bazigos A., Ionescu A. M. 2015 “Compact modeling of DG-Tunnel FET for Verilog-A implementation,” [in Proceeding of 2015 45th European Solid State Device Research Conference (ESSDERC)] P.40-43 google
  • 5. Tanaka C., Adachi K., Fujimatsu M., Kondo Y., Hokazono A., Kawanaka S. 2016 “Implementation of TFET SPICE model for ultra-low power circuit analysis,” [IEEE Journal of the Electron Devices Society] google doi
  • 6. Bardon M. G., Neves H. P., Puers R., Van Hoof C. 2010 “Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions,” [IEEE Transactions on Electron Devices] Vol.57 P.827-834 google doi
  • 7. Khakifirooz A., Nayfeh O. M., Antoniadis D. 2009 “A simple semiempirical short-channel MOSFET current?voltage model continuous across all regions of operation and employing only physical parameters,” [IEEE Transactions on Electron Devices] Vol.56 P.1674-1680 google doi
  • 8. Zhang L., He J., Chan M. 2012 “A compact model for double-gate tunneling field-effect-transistors and its implications on circuit behaviors,” [in Proceeding of 2012 IEEE International Electron Devices Meeting (IEDM)] P.1-4 google
  • 9. Vishnoi R., Kumar M. J. 2014 “Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport,” [IEEE Transactions on Electron Devices] Vol.61 P.1936-1942 google doi
  • 10. Wan J., Le Royer C., Zaslavsky A., Cristoloveanu A. 2011 “A tunneling field effect transistor model combining interband tunneling with channel transport,” [Journal of Applied Physics] Vol.110 google doi
  • 11. Xu H., Dai Y., Li N., Xu J. 2015 “A 2-D semi-analytical model of double-gate tunnel field-effect transistor,” [Journal of Semiconductors] Vol.36 P.1-7 google
  • 12. Wang J., Wu C., Huang Q., Wang C., Huang R. 2014 “A closedform capacitance model for tunnel FETs with explicit surface potential solutions,” [Journal of Applied Physics] Vol.116 google
  • 13. Gholizadeh M., Hosseini S. E. 2014 “A 2-D analytical model for double-gate tunnel FETs,” [IEEE Transactions on Electron Devices] Vol.61 P.1494-1500 google doi
  • 14. Prabhat V., Dutta A. K. 2016 “Analytical surface potential and drain current models of dual-metal-gate double-gate tunnel-FETs,” [IEEE Transactions on Electron Devices] Vol.63 P.2190-2196 google doi
  • 15. Zhang L., Lin X., He J., Chan M. 2012 “An analytical charge model for double-gate tunnel FETs,” [IEEE Transactions on Electron Devices] Vol.59 P.3217-3223 google doi
  • 16. Wu C., Huang R., Huang Q., Wang C., Wang J., Wang Y. 2014 “An analytical surface potential model accounting for the dualmodulation effects in tunnel FETs,” [IEEE Transactions on Electron Devices] Vol.61 P.2690-2696 google doi
  • 17. Kane E. O. 1960 “Zener tunneling in semiconductors,” [Journal of Physics and Chemistry of Solids] Vol.12 P.181-188 google doi
  • 18. Wang C., Wu C., Wang J., Huang Q., Huang R. 2015 “Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling,” [Science China Information Sciences] Vol.58 P.1-8 google
  • 19. 2005 SILVACO International, ATLAS II Framework (ver. 5.10.2.R) google
  • [Table 1.] Electrical and performance parameter description
    Electrical and performance parameter description
  • [Fig. 1.] (a) Schematic of TFET and (b) band diagram of TFET showing the TFET both in its on state (left) and in its off state (right).
    (a) Schematic of TFET and (b) band diagram of TFET showing the TFET both in its on state (left) and in its off state (right).
  • [] 
  • [] 
  • [] 
  • [] 
  • [] 
  • [] 
  • [] 
  • [] 
  • [] 
  • [] 
  • [] 
  • [] 
  • [Fig. 2.] Illustration of method for extracting Ak /Bk values as a function of Vds (=1.0 V). Here, Eavg is a function of Vgs. Ids is obtained from TCAD simulation. Ak /Bk can be obtained as the intercept and slope, respectively, of the linear region of the graph shown above.
    Illustration of method for extracting Ak /Bk values as a function of Vds (=1.0 V). Here, Eavg is a function of Vgs. Ids is obtained from TCAD simulation. Ak /Bk can be obtained as the intercept and slope, respectively, of the linear region of the graph shown above.
  • [Fig. 3.] (a) Ak values as a function of Vds and (b) Bk values as a function of Vds. Symbols in (a): extracted from intercept of (10). Symbols in (b): extracted from slope of log of (10). Lines in (a) and (b): fit for the extracted values given by (11) and (12) for device with εox =3.9 (blue), and 21 (orange), respectively. Other device parameters are the same as mentioned in Table 1.
    (a) Ak values as a function of Vds and (b) Bk values as a function of Vds. Symbols in (a): extracted from intercept of (10). Symbols in (b): extracted from slope of log of (10). Lines in (a) and (b): fit for the extracted values given by (11) and (12) for device with εox =3.9 (blue), and 21 (orange), respectively. Other device parameters are the same as mentioned in Table 1.
  • [Fig. 4.] Surface potential profile for device 1 along channel length for Vgs ranging from ±0.25 to ±1 V, and Vds held constant. (a) Vds =±0.25 V. (b) Vds =±1.0 V. Symbols: TCAD, Lines: Model. Open symbols and solid lines: N-type DGTFET, filled symbols and dashed lines: P-type DGTFET. Here ‘+’ and ‘?’ indicate bias for N-DGTFET and P-DGTFET, respectively.
    Surface potential profile for device 1 along channel length for Vgs ranging from ±0.25 to ±1 V, and Vds held constant. (a) Vds =±0.25 V. (b) Vds =±1.0 V. Symbols: TCAD, Lines: Model. Open symbols and solid lines: N-type DGTFET, filled symbols and dashed lines: P-type DGTFET. Here ‘+’ and ‘?’ indicate bias for N-DGTFET and P-DGTFET, respectively.
  • [Fig. 5.] Surface potential profile for device 2 along channel length for Vgs ranging from ±0.25 to ±1 V, and Vds held constant. (a) Vds =±0.25 V. (b) Vds =±1.0 V. Symbols: TCAD, Lines: Model. Open symbols and solid lines: N-DGTFET, filled symbols and dashed lines: P-DGTFET. Here ‘+’ and ‘?’ indicate the bias for the N-DGTFET and P-DGTFET, respectively.
    Surface potential profile for device 2 along channel length for Vgs ranging from ±0.25 to ±1 V, and Vds held constant. (a)  Vds =±0.25 V. (b) Vds =±1.0 V. Symbols: TCAD, Lines: Model. Open symbols and solid lines: N-DGTFET, filled symbols and dashed lines: P-DGTFET. Here ‘+’ and ‘?’ indicate the bias for the N-DGTFET and P-DGTFET, respectively.
  • [Fig. 6.] Ids V Vgs for device 1 (N-DGTFET), for different Vds ranging from 0.15 to 1.0 V with increments of 0.25 V. Symbols: TCAD, Lines: Model.
    Ids V Vgs for device 1 (N-DGTFET), for different Vds ranging from 0.15 to 1.0 V with increments of 0.25 V. Symbols: TCAD, Lines: Model.
  • [Fig. 7.] Ids V Vgs for device 1 (P-DGTFET), for different Vds ranging from -0.15 to -1.0 V with increments of -0.25 V. Symbols: TCAD, Lines: Model.
    Ids V Vgs for device 1 (P-DGTFET), for different Vds ranging from -0.15 to -1.0 V with increments of -0.25 V. Symbols: TCAD, Lines: Model.
  • [Fig. 8.] Ids V Vds for device 1, shown for both N-DGTFET, and P-DGTFET, for different Vgs values ranging from ±0.25 V to ±1.0 V in increments of ±0.25 V. Symbols: TCAD, Lines: Model. Open symbols and solid lines: N-DGTFET, Filled symbols and dashed lines: P-DGTFET. Here ‘+’ and ‘?’ indicate bias for N-DGTFET and P-DGTFET, respectively.
    Ids V Vds for device 1, shown for both N-DGTFET, and P-DGTFET, for different Vgs values ranging from ±0.25 V to ±1.0 V in increments of ±0.25 V. Symbols: TCAD, Lines: Model. Open symbols and solid lines: N-DGTFET, Filled symbols and dashed lines: P-DGTFET. Here ‘+’ and ‘?’ indicate bias for N-DGTFET and P-DGTFET, respectively.
  • [Fig. 9.] Ids V Vgs for device 1 (N-DGTFET), for different Vds ranging from 0.15 to 1.0 V with increments of 0.25 V. Symbols: TCAD, Lines: Model.
    Ids V Vgs for device 1 (N-DGTFET), for different Vds ranging from 0.15 to 1.0 V with increments of 0.25 V. Symbols: TCAD, Lines: Model.
  • [Fig. 10.] Ids V Vgs for device 2 (P-DGTFET), for different Vds ranging from -0.15 to -1.0 V with increments of -0.25 V. Symbols: TCAD, Lines: Model.
    Ids V Vgs for device 2 (P-DGTFET), for different Vds ranging from -0.15 to -1.0 V with increments of -0.25 V. Symbols: TCAD, Lines: Model.