General SPICE Modeling Procedure for DoubleGate Tunnel FieldEffect Transistors
 Author: Najam Syed Faraz, Tan Michael Loong Peng, Yu Yun Seop
 Publish: Journal of information and communication convergence engineering Volume 14, Issue2, p115~121, 30 June 2016

ABSTRACT
Currently there is a lack of literature on SPICElevel models of doublegate (DG) tunnel fieldeffect transistors (TFETs). A DG TFET compact model is presented in this work that is used to develop a SPICE model for DG TFETs implemented with VerilogA language. The compact modeling approach presented in this work integrates several issues in previously published compact models including ambiguity about the use of tunneling parameters
A _{k} andB _{k}, and the use of a universal equation for calculating the surface potential of DG TFETs in all regimes of operation to deliver a general SPICE modeling procedure for DG TFETs. The SPICE model of DG TFET captures the drain currentgate voltage (I _{ds}V _{gs}) characteristics of DG TFET reasonably well and offers a definite computational advantage over TCAD. The general SPICE modeling procedure presented here could be used to develop SPICE models for any combination of structural parameters of DG TFETs.

KEYWORD
Compact model , Drain current , Inverter , Potential profile , TFET , Verilog

I. INTRODUCTION
In recent times the tunneling fieldeffect transistor (TFET) has attracted a great deal of attention owing to its subthreshold slope (SS) < 60 mV/dec. As such, it is regarded as one of the potential replacements for conventional CMOS technology, which is facing many fundamental challenges in sustaining further technology scaling [1]. The operation principle of the TFET is based on bandtobandtunneling (BTBT), which enables it to achieve a steeper SS. A TFET can be fabricated using existing semiconductor technologies, and for these reasons TFET is regarded as a very promising technology.
SPICE modeling has been the benchmark of logic and circuitlevel simulation and has played a vital part in the development of current CMOS devices. In order to investigate and better understand the performance of TFETbased logic devices and circuits, a fast compact model with medium accuracy needs to be developed. The literature in this regard is lacking. There are a few TFET Verilog models that exist [25]. However, [2,3] are lookuptable based models that require several fitting parameters; further, the fitting process in [2] is iterative. The model of [4] ignores the source and drain depletion lengths, which limits the accuracy of the model [6]. In the Verilog model of [5], the TFET drain current is found using a shortchannel MOSFET model [7], which is physically incorrect for a TFET. Whereas [8] is a standardreference TFET compact model, there is ambiguity in the use of tunneling parameters
A _{k} andB _{k} used in the drain current expression of the model. The actualA _{k} andB _{k} values used in [8,9] are not clear. While a method to extract theA _{k} andB _{k} values from the data of drain currentgate voltage (I _{ds}V _{gs}) characteristics is presented in [10,11], the model of [10] and also [12] is for bulk TFET. Further, the model of [11] is piecewise with different equations for saturation and linear regimes of operation which is not suitable for SPICE modeling. Some other models [13,14] neglect the source depletion region, which at highV _{gs} becomes significant [6] and should not be ignored. Each of these issues restricts the accuracy of the existing models. In light of the above, there is a lack of a clear and accurate TFET compact modeling approach integrating all of the abovementioned issues from a SPICE model point of view.This lack of a concise modeling approach integrating all of the above mentioned issues impedes development of SPICE models for TFETs. In this work, we devise a clear doublegate (DG) TFET modeling approach and use it to develop a DGTFET VerilogA model implemented in SPICE.
The paper is organized in the following sections. Section II explains the DGTFET compact modeling part. Section III includes the verification of the model. The conclusion is presented in Section IV.
II. TFET COMPACT MODEL
This section explains the DGTFET compact model. All the parameters used in the literature are mentioned in Table 1 given below.
Fig. 1 shows the schematic of an Ntype DGTFET (NDGTFET). An NDGTFET comprises a P^{+} source region with doping, an N^{+} drain region, and an intrinsic channel.
From a modeling point of view, a DGTFET is divided into 3 regions. Region I is composed of a source depletion region with
L _{1} highlighting the length of the source depletion region as shown in Fig. 1. Region II comprises the tunneling junction between the source and channel withx =0 being at the boundary of both regions.Here,
L _{2} in region II specifies the length of the channel depletion region as indicated in Fig. 1(a). Region III comprises the transport region, where the charge carriers that tunnel through the tunneling barrier are transported to the drain by driftdiffusion with transport along the direction of thex axis. Fig. 1(b) shows the band diagram of the DGTFET in on (left) and off (right) states.A Poisson equation is solved in regions I and II with the help of boundary conditions to find the surface potentials in regions I and II. Following [15], the surface potentials
φ _{s1} andφ _{s2} are given bywhere
V _{fbs} is the flatband voltage. The surface potential in region III, i.e.φ _{dg}, is calculated from [16] after making necessary adjustments for a DGTFET. The depletion lengths of regions I and II, i.e.L _{1} andL _{2}, can be found by solving (1) and (2) together using their continuous potential and electric field atx =0.L _{1} andL _{2} are given by the following equations [15]:The potential at the internal boundary between region I and II is given by [15],
where is a constant in (5).
The drain current of the DGTFET can be given by the following expression obtained after making simplifying approximations [9,11,17].
Here the average electric field is given by [814],
The minimum tunneling distance
l _{tw} could be described as the distance between the end of the source depletion region (i.e., region I) [8,10,11] and the point in region II where the surface potential has a value equal to the bandgap of the channel material.l _{tw} can be given by [8],In (8),
φ _{min} can be found by setting∂l_{tw} /∂φ_{s} _{2} = 0 [8,18] and is given byIn (6),
A _{k} andB _{k} are found [10,11] by taking the logarithm on both sides, such that it can be written asA _{k} andB _{k} can be extracted from (10), for a fixedV _{ds} bias value as the intercept and slope of (10). HereI _{ds} is obtained from the TCAD simulation results [19], andE _{avg} is calculated from (7).The extraction procedure for a fixed
V _{ds} value is shown in Fig. 2, whereas extractedA _{k} andB _{k} values and their polynomial fits (lines) are shown in Fig. 3(a) and (b), respectively, as a function ofV _{ds}. Equations for secondorder polynomial fits forA _{k} andB _{k} are given below.where
A_{0}, A_{1}, A_{2}, B_{0}, B_{1} , andB_{2} are the fitted parameters.Eqs. (11) and (12) were used to develop the SPICE model for the DGTFET, and are a very important component of the SPICE model. While only 2 dielectric constants were considered in this work, the procedure presented in this work is general and could be used to develop SPICE models for any combination of DGTFET device parameters mentioned in Table 1.
III. MODEL VERIFICATION
Two types of devices were considered in this section. Equivalent parameters (mentioned in Table 1) were considered for both the devices except for
ε _{ox} =3.9 with device 1 andε _{ox} =21 with device 2. Ntype (NDGTFET) and Ptype (PDGTFET) versions of both devices were considered in this work. For simplicity, the equivalent hole and electron tunneling mass was used for the PDGTFET and NDGTFET, respectively. In addition, the work function difference for both the PDFTFET (W _{fg} =5.24 eV) and NDGTFET (W _{fg} =4.20 eV) were adjusted in TCAD such that theI _{ds} V _{gs} characteristics obtained were equivalent. Fig. 4 shows the potential profile along the channel length for both Ntype device 1 and Ptype device 1 calculated from the model (lines) compared with the potential profile obtained from the simulator (symbols) forV _{gs} ranging from ±0.25 to ±1 V with increments of ±0.25 V andV _{ds} held constant atV _{ds} = ±0.25 V (Fig. 4(a)) andV _{ds} = ±1.0 V (Fig. 4(b)). Here ‘+’ and ‘–’ indicate the bias for the NDGTFET and PDGTFET, respectively. The open symbols and solid lines indicate the potential for the NDGTFET. The filled symbols and dashed lines indicate the potential for the PDGTFET. The calculated potential profile is in good agreement with that obtained from the simulator.The potential profile from Fig. 4(a) with
V _{ds} =±0.25 V clearly shows the surface potential increasing linearly with increasingV _{gs} and also becoming steeper. This increases the electric field at the sourcechannel junction resulting in reducing the minimum tunneling distance.Fig. 4(b), which shows the potential profile for a higher
V _{ds} =±1.0 V, demonstrates that with increasing drain bias, the inversion electron concentration is reduced in the channel, allowing for effective unpinning of the channel fermi level.Fig. 5(a) and (b) show the potential profile for Ntype (open symbols [TCAD], and solid lines [model]), and Ptype (filled symbols [TCAD] and dashed lines [model]) device 2, which has a higher
ε _{ox} =21 at the sameV _{gs} andV _{ds} bias conditions as Fig. 4(a) and (b). Fig. 5(a) and (b) clearly show stronger saturation as compared to Fig. 4(a), and (b), respectively, and much shorter channel depletion lengths. This demonstrates that the gate field is stronger in the case of a higherε _{ox}. Overall, the model results compare very well with simulation results.Figs. 6 and 7 show
I _{ds} V _{gs} characteristics for Ntype device 1 and Ptype device 1, respectively, for aV _{ds} ranging from ±0.15 to ±1.0 V. Here ‘+’ and ‘–’ indicate bias for the NDGTFET and PDGTFET, respectively. Both the model (lines) and simulation (symbols) show good agreement.The parameters for
A _{k} andB _{k} are fitted asA _{0} = 2.1195×10^{18},A _{1} = 1.0797×10^{19},A _{2} = 4.3336×10^{18},B _{0} = 2.4356×10^{7},B _{1} = 2.7468×10^{7}, andB _{2} = 1.6002×10^{7} shown as blue lines in Fig. 3(a) and (b), respectively.Fig. 8 shows
I _{ds} V _{gs} characteristics for both Ntype and Ptype device 1, forV _{gs} values ranging from ±0.25 to ±1.0 V. Open (NDGTFET) and filled symbols (PDGTFET) indicate simulation results, and solid (NDGTFET) and dashed lines (PDGTFET) indicate results from the model. Reasonable agreement can be observed between the model and simulation results, particularly for highV _{gs}, which is a feature ofE _{avg} based models [9]. Here the same fitting parameters forA _{k} andB _{k} were used as those in Figs. 6 and 7.Figs. 9 and 10 show
I _{ds} V _{gs} characteristics for Ntype device 2 and for Ptype device 2, respectively, calculated from the model (lines) usingA _{k} andB _{k} with the parameters fitted asA _{0} = 3.8153×10^{19},A _{1} = 5.2005×10^{18},A _{2} = 1.3295×10^{19},B _{0} = 3.0917×10^{7},B _{1} = 2.2843×10^{7}, andB _{2} = 1.597×10^{7} as shown by the orange lines in Fig. 3(a) and (b), respectively, with the simulation (symbols). The model captures very well the effect of varying device structural parameters on device characteristics. A much higherI _{ds} is obtained for device 2, which in agreement with Fig. 5, demonstrating that due to a thinner effective oxide, the increased gate field across the tunneling junction results in increased current.IV. CONCLUSIONS
A SPICE model for a DGTFET is presented in this work. The method of Zhang et al. [8,15] was adopted to obtain the DGTFET surface potential, and the method developed by [4] was used to extract the
A _{k} andB _{k} values for 1) a device with conventional SiO_{2} as a dielectric and 2) for a highκ device withε _{ox} =21. The extractedA _{k}/B _{k} values were fitted using a seconddegree polynomial. Using the fitting equations, a DGTFET SPICE model was developed. SPICE simulation results were presented for the DGTFET. By finding relevantA _{k}/B _{k} fits, the procedure presented in this work could be used to expand the current SPICE model to any combination of DGTFET structural parameters. Future expansion of the current SPICE model includes using constantA _{k}/B _{k} values as a function ofV _{ds} to achieveI _{ds} V _{gs} saturation in order to enable SPICE simulation for a wide range of logic devices including inverters. The SPICE model presented here does not need various fitting parameters, unlike [2,3], and is easy to use. The SPICE model compares very well with TCAD simulation results and offers a definite computational advantage over TCAD.

[Table 1.] Electrical and performance parameter description

[Fig. 1.] (a) Schematic of TFET and (b) band diagram of TFET showing the TFET both in its on state (left) and in its off state (right).

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[Fig. 2.] Illustration of method for extracting Ak /Bk values as a function of Vds (=1.0 V). Here, Eavg is a function of Vgs. Ids is obtained from TCAD simulation. Ak /Bk can be obtained as the intercept and slope, respectively, of the linear region of the graph shown above.

[Fig. 3.] (a) Ak values as a function of Vds and (b) Bk values as a function of Vds. Symbols in (a): extracted from intercept of (10). Symbols in (b): extracted from slope of log of (10). Lines in (a) and (b): fit for the extracted values given by (11) and (12) for device with εox =3.9 (blue), and 21 (orange), respectively. Other device parameters are the same as mentioned in Table 1.

[Fig. 4.] Surface potential profile for device 1 along channel length for Vgs ranging from ±0.25 to ±1 V, and Vds held constant. (a) Vds =±0.25 V. (b) Vds =±1.0 V. Symbols: TCAD, Lines: Model. Open symbols and solid lines: Ntype DGTFET, filled symbols and dashed lines: Ptype DGTFET. Here ‘+’ and ‘？’ indicate bias for NDGTFET and PDGTFET, respectively.

[Fig. 5.] Surface potential profile for device 2 along channel length for Vgs ranging from ±0.25 to ±1 V, and Vds held constant. (a) Vds =±0.25 V. (b) Vds =±1.0 V. Symbols: TCAD, Lines: Model. Open symbols and solid lines: NDGTFET, filled symbols and dashed lines: PDGTFET. Here ‘+’ and ‘？’ indicate the bias for the NDGTFET and PDGTFET, respectively.

[Fig. 6.] Ids V Vgs for device 1 (NDGTFET), for different Vds ranging from 0.15 to 1.0 V with increments of 0.25 V. Symbols: TCAD, Lines: Model.

[Fig. 7.] Ids V Vgs for device 1 (PDGTFET), for different Vds ranging from 0.15 to 1.0 V with increments of 0.25 V. Symbols: TCAD, Lines: Model.

[Fig. 8.] Ids V Vds for device 1, shown for both NDGTFET, and PDGTFET, for different Vgs values ranging from ±0.25 V to ±1.0 V in increments of ±0.25 V. Symbols: TCAD, Lines: Model. Open symbols and solid lines: NDGTFET, Filled symbols and dashed lines: PDGTFET. Here ‘+’ and ‘？’ indicate bias for NDGTFET and PDGTFET, respectively.

[Fig. 9.] Ids V Vgs for device 1 (NDGTFET), for different Vds ranging from 0.15 to 1.0 V with increments of 0.25 V. Symbols: TCAD, Lines: Model.

[Fig. 10.] Ids V Vgs for device 2 (PDGTFET), for different Vds ranging from 0.15 to 1.0 V with increments of 0.25 V. Symbols: TCAD, Lines: Model.