Microwave Negative Group Delay Circuit: FilterSynthesis Approach

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  • ABSTRACT

    This paper presents the design of a negative group delay circuit (NGDC) using the filter synthesis approach. The proposed design method is based on a frequency transformation from a low-pass filter (LPF) to a bandstop filter (BSF). The predefined negative group delay (NGD) can be obtained by inserting resistors into resonators. To implement a circuit with a distributed transmission line, a circuit conversion technique is employed. Both theoretical and experimental results are provided for validating of the proposed approach. For NGD bandwidth and magnitude flatness enhancements, two second-order NGDCs with slightly different center frequencies are cascaded. In the experiment, group delay of 5.9±0.5 ns and insertion loss of 39.95±0.5 dB are obtained in the frequency range of 1.935–2.001 GHz.


  • KEYWORD

    Bandstop Filter , Frequency Transformation , Filter Approach , Low Pass Filter Prototype , Negative Group Delay

  • I. INTRODUCTION

    Most media exhibit a normal propagation characteristic called subluminal velocity, where the speed of propagation of individual time-harmonic components is slower than the speed of light,c, in vacuum at all frequencies. However, in a specific and narrow frequency band of signal attenuation or at an anomalous dispersion frequency, the group velocity is observed to be greater than c. This abnormal wave propagation is called superluminal velocity or negative group velocity [1,2]. At first, the concept of superluminal velocity seems to defy causality. However, many practical experiments have shown that the concept of superluminal velocity does not violate the definition of a causal system [35].

    One example of the concept of superluminal velocity is the negative group delay (NGD); this refers to the phenomenon whereby an electromagnetic wave traverses a medium in such a manner that its amplitude envelope is advanced rather than delayed [6]. Recently, many studies have designed negative group delay circuits (NGDCs) and used them in practical applications such as enhancing the efficiency of a feed-forward amplifier [7], shorting delay lines [8], realizing non-Foster reactive elements [9], and minimizing beam-squint problems in series-fed antenna arrays systems [10].

    The conventional design method of active and passive NGDCs is based on only single RLC resonators [11-18]. The NGD bandwidth and magnitude flatness should be as wide as possible for applications in RF circuits and systems. However, conventional NGDCs suffer from smaller NGD bandwidth and poor magnitude flatness. To overcome these problems, some studies have attempted to design NGDCs using different methods such as cascading the number of resonators with slightly different center frequencies [16] and cross-coupling between resonators [17].

    In this study, a filter synthesis approach is applied to design an NGDC. In this proposed method, circuit element values are obtained from low-pass filter (LPF) prototypes by applying a frequency transformation.

    II. DESIGN EQUATIONS ANALYSIS

    Fig. 1(a) shows the Butterworth LPF prototype. The element values of the LPF are obtained as follows [19].

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    where N is the order of the filter. Fig. 1(b) shows the structure of the proposed NGDC. The lumped elements of the proposed NGDC are easily obtained from the LPF by applying the following frequency transformation [19].

    image

    where Δ and ω0 are the 3-dB fractional bandwidth (FBW) and center frequency of the NGDC, respectively. The elements values of the shunt-series branch (Lssi,Cssi) are given as follows.

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    where Z0, gi, and ω0 are the port impedance, i-th prototype element value, and center frequency of the NGDC, respectively. Similarly, the element values of the series-parallel branch (Lspj, Cspj) are given as follows.

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    The resistors are inserted into the shunt and series resonators to obtain the required NGD. The values of these resistors are obtained by analyzing the shunt-series and series-parallel branch elements [18], respectively. The resistances in the shunt-series branch of the NGDC for the required NGD are given as follows.

    image

    where τ and αare the GD and correction factor, respectively. Similarly, the resistance in the series-parallel branch of the NGDC is given are given as follows.

    image

    A correction factor α is substituted into (5) and (6) to consider the fact that each resonator contributes to GD and increases the overall GD so that it is higher than the required value for the overall circuit as N increases. Substituting α into these equations compensates for the deviation from the required value.

    Fig. 2 shows the synthesized results of the NGDC with different numbers of stages N. The specifications and calculated circuit element values of the proposed NGDC are shown in Tables 1 and 2, respectively. As shown in Fig 2(a), the NGD bandwidth increases slightly with N. However, the signal attenuation (magnitude of S21) also increases for the same maximum achievable GD, which can be compensated using general purpose gain amplifiers. Therefore, the signal attenuation (SA) of the proposed NGDC should be as small as possible so that the number of gain amplifiers can be reduced. The NGD bandwidth and maximum SA of the simulated circuits are shown in Table 3. From Table 3, it is clear that a trade-off between the NGD, insertion loss (magnitude of S21), NGD bandwidth, and number of stages N should be considered. Fig. 2(b) shows the phase characteristics of the NGDC with N=2 and N=3. As seen from Fig. 2(b), the phase of S21 increases with frequency (positive slope) in the case of an NGDC, indicting the presence of NGD.

    The proposed NGDC shown in Fig. 1(b) consists of both shunt-series (Rssk, Lssk, Cssk) and series-parallel (Rspk,Lspk, Cspk) lumped elements. A series parallel-resonator is difficult to implement at the microwave frequencies owing to the limited feasibility of the designed lumped elements.

    To overcome this problem, the circuit conversion technique can be applied to convert the series-parallel lumped elements (Rspk, Lspk, Cspk) into shunt-series lumped elements (Rcssi, Lcssi, Ccssi) using admittance inverters (J-inverters), as shown in Fig. 3. The corresponding conversion relations are given as follows.

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    Theoretically, the value of the J-inverter can be chosen arbitrary. However, in practice, J-inverters should be chosen carefully because their physical dimensions must be realizable without any difficulties. Fig. 4 shows the overall structure of proposed NGDC; it consists of J-inverters and shunt-series LC resonators. The J-inverters can be implemented using quarter-wavelength transmission lines. The shunt-series LC resonators can be implemented using either short-circuited half-wavelength or open-circuited quarter-wavelength resonators [19].

    III. SIMULATION AND EXPERIMENTAL RESULTS

    To validate the proposed design method, a second order NGDC was designed and fabricated on a substrate with dielectric constant (εr) of 2.2 and thickness (h) of 31 mils. The goal was to design an NGDC with GD of -6 ns at a center frequency of 1.97 GHz. In this work, J-inverters and shunt-series LC resonators are implemented with λ/4 transmission line and short-circuited λ/2 transmission lines, respectively.

    As shown by the results in the previous sections, the NGD bandwidth of the proposed circuit is narrow. One of the ways to increase the NGD bandwidth is to increase N. However, increasing N cannot provide a large increase in the NGD bandwidth, as shown in Fig. 2; however, the insertion loss is increased. Another way to employ an NGDC with a wider NGD bandwidth is to cascade NGDCs operating at slightly different center frequencies as shown in Fig. 5. Therefore, in this study, to enhance the NGD bandwidth and magnitude flatness, two-stage NGDCs with center frequencies of 1.932 and 2 GHz and FWB of 10% are cascaded. Fig. 5 shows the physical dimensions of the designed NGDC.

    Fig. 6 shows the simulation and measurement results of the fabricated cascaded two-stage NGDC and comparison with NGDCs with N=4 and N=5. The measurement results agreed well with the simulation results. The measured GD time and insertion loss were -5.9±0.5 ns and 39.95±0.5 dB, respectively, in the frequency range of 1.935–2.001 GHz.

    These results also show that the NGD bandwidth and magnitude flatness are wider than those of NGDCs with N = 4 and N=5 and conventional NGDCs [11-17]. However, the trade-off among the NGD, bandwidth and magnitude flatness should be considered. The small fraction of NGD and insertion loss differences between the simulation and the measurement are due to the parasitic components of the resistors. Fig. 7 shows a photograph of the fabricated NGDC.

    Table 4 shows a performance comparison of the proposed NGDC with those in previous works. Owing to the trade-off among the maximum achieved GD (GDmax), maximum SA (SAmax) and NGD bandwidth (NGD-BW), the figure of merit (FOM) of NGD circuits can be defined as follows.

    image

    As seen from Table 4, the proposed NGDC provides the highest FOM and best performance in terms of GD/magnitude flatness even though the SA is higher than of some previously proposed NGDCs [13,16-18].

    IV. CONCLUSION

    In this paper, a filter synthesis approach is applied to design a NGDC. The circuit elements of the proposed filter can be obtained from LPF prototype elements. The proposed circuit was implemented with a distributed transmission line using a circuit conversion technique. An experiment was performed to validate the proposed design method. The measurement results agreed well with the simulation results. The proposed NGDC shows the highest FOM, large negative group delay, good magnitude flatness, and wider negative group delay-bandwidth.

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  • [Fig. 1.] (a) Low-pass filter prototype and (b) proposed structure of a negative group delay circuit.
    (a) Low-pass filter prototype and (b) proposed structure of a negative group delay circuit.
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  • [Fig. 2.] Synthesized results of proposed negative group delay circuit (NGDC) with different numbers of stages N: (a) group delay/magnitude and (b) phase characteristics.
    Synthesized results of proposed negative group delay circuit (NGDC) with different numbers of stages N: (a) group delay/magnitude and (b) phase characteristics.
  • [Table 1.] Specifications of negative group delay circuits
    Specifications of negative group delay circuits
  • [Table 2.] Element values of negative group delay circuits (NGDCs) with GD=-6 ns
    Element values of negative group delay circuits (NGDCs) with GD=-6 ns
  • [Table 3.] Calculated NGD BW and SAmax for different numbers of filter stages
    Calculated NGD BW and SAmax for different numbers of filter stages
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  • [Fig. 3.] Series-parallel to shunt-series circuit transformation.
    Series-parallel to shunt-series circuit transformation.
  • [Fig. 4.] Proposed negative group delay circuit with J-inverters and shunt-series RLC circuits.
    Proposed negative group delay circuit with J-inverters and shunt-series RLC circuits.
  • [Fig. 5.] Structure of cascaded two-stage negative group delay circuit (NGDC) for NGD bandwidth and magnitude flatness enhancements. Physical dimensions: L1=22.90, L2=26.10, L3=5, L4=55.2, L5=57.36, W1=3.54, W2=0.32, W3=0.54, W4=0.36, W5=0.58 (unit: mm).
    Structure of cascaded two-stage negative group delay circuit (NGDC) for NGD bandwidth and magnitude flatness enhancements. Physical dimensions: L1=22.90, L2=26.10, L3=5, L4=55.2, L5=57.36, W1=3.54, W2=0.32, W3=0.54, W4=0.36, W5=0.58 (unit: mm).
  • [Fig. 6.] Simulated and measurement results of cascaded two-stage negative group delay circuit.
    Simulated and measurement results of cascaded two-stage negative group delay circuit.
  • [Fig. 7.] Photograph of fabricated negative group delay circuit.
    Photograph of fabricated negative group delay circuit.
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  • [Table 4.] Performance comparison of the proposed NGDC with those in previous works
    Performance comparison of the proposed NGDC with those in previous works