A High Gain and High Harmonic Rejection LNA Using High Q Series Resonance Technique for SDR Receiver

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  • ABSTRACT

    This paper presents a high gain and high harmonic rejection low-noise amplifier (LNA) for software-defined radio receiver. This LNA exploits the high quality factor (Q) series resonance technique. High Q series resonance can amplify the in-band signal voltage and attenuate the out-band signals. This is achieved by a source impedance transformation. This technique does not consume power and can easily support multiband operation. The chip is fabricated in a 0.13-μm CMOS. It supports four bands (640, 710, 830, and 1,070MHz). The measured forward gain (S21) is between 12.1 and 17.4 dB and the noise figure is between 2.7 and 3.3 dB. The IIP3 measures between -5.7 and -10.8 dBm, and the third harmonic rejection ratios are more than 30 dB. The LNA consumes 9.6 mW from a 1.2-V supply.


  • KEYWORD

    High Gain , High Harmonic Rejection , High Quality Factor Series Resonance , Impedance Transformation , SDR.

  • Ⅰ. INTRODUCTION

    Recently, the number of wireless communication services has been increasing steadily. With an ever-increasing number of frequency bands and diverse wireless communication standards, front-end complexity and costs have risen. Therefore, the conventional receiver architecture requires more chips. Consequently, a software-defined radio (SDR) receiver is needed to reduce complexity and costs [1]. An SDR receiver can accomplish this, but it can also suffer from outof-band interferences because it deals with wideband signals at the RF front-end [2].

    Among various mixer architectures in SDR receivers, a hard-switching mixer is preferred, due to its superior gain and low noise characteristic [3,4].

    However, the desired signal is aliased with the interferers which are located around local oscillator (LO) odd order harmonic frequencies when down-converted to the baseband at the hard-switching mixer stage. Multi-phase mixers have been suggested to suppress RF signals around LO harmonics [3,5,6]; however, they have the following drawbacks: 1) the seventh harmonic is not rejected and causes aliasing; 2) the third and fifth harmonic rejection (HR) performance is restricted by amplitude and phase mismatches; and 3) the complexity and size increase. The third HR ratio at the mixer stage is practically constrained to 30 to 40 dB, but much more rejection is needed to attenuate harmonic interferences with -40 to 0 dBm power down to the noise floor [7]. Therefore, a high HR ratio is required before the mixer stage.

    In [8], a design technique is provided for high HR; however, this does not address the resistance of the inductor or the induced gate noise. In [9], the research also neglects these noise sources and the fabricated and measured results are not described. The present paper analyzes a high Q resonance technique with these noise sources and provides a design guideline.

    In this paper, Section II discusses the high Q series resonance technique, while Section III describes the circuit implementation in detail. Section IV shows the experimental results of the demonstrated low-noise amplifier (LNA) circuit. Finally, a conclusion is given in Section V.

    Ⅱ. THE HIGH Q SERIES RESONANCE TECHNIQUE

    A MOSFET senses a voltage at the gate-source capacitor. Series resonance amplifies the in-band signal voltage and attenuates the out-band signal voltage at capacitor. Among the LNA architectures that use series resonance, the inductively degenerated LNA (L-CS LNA) [10] is popular and widely used. However, the voltage gain and HR are limited because the Q is constrained. A source degeneration technique simply provides input matching, although it decreases the Q.

    Techniques for improving the Q of the LNA input passive network have previously been presented [8]. In [8], theoretically, a value of Q that can be obtained approximately two times larger than the L-CS LNA can be obtained when all parameters and conditions are same except input network. This is achieved by abandoning the degeneration inductor. However, an even higher Q is still needed to attain sufficiently high gain and a high HR ratio with low power operation. Moreover, this study did not consider the resistance of the inductor or the induced gate noise.

    A high Q series resonance LNA (HQ-LNA) can overcome these problems, as shown in Fig. 1. A source impedance transformation provides higher Q resonance, as well as high gain and high HR. A source impedance transformation can be attained by a variety of methods, and a transmission line is a good approach. A multiband operation is also easily achieved by adjusting the resonance frequency, and this can be accomplished by changing the gate-source capacitor Ctot. The smallest Ctot equals Cgs (S1 and S2 are off), while largest Ctot equals Cgs + C1 + C2 (S1 and S2 are on).

    Fig. 2 shows the equivalent circuit of the proposed technique. The source voltage vs and the source impedance Rs are transformed to vst and Zst, respectively. These values are determined by the transmission line parameters, which are the characteristic impedance Z0 and length of the line lTL. Therefore, a transmission line with proper characteristic impedance and length can produce a low source resistance, Rst, which is the resistive part of Zst. As a result, high Q series resonance is obtained. An inductor, Lg, is used for resonance with capacitance, and the Rl,g is the resistance of the inductor Lg.

    The following analyses (gain and harmonic rejection ratio analysis) were performed with exclusion of the bonding effect. In this work, we minimized this effect by carried out multiple down bonding. Parasitic capacitances (routing parasitic capacitances, pad capacitances) also result in resistive input. If the bonding effect generates several tens of resistive impedance, then the effect must be included in the analysis. In that case, the Rl,g changes to Rl,g + Rbond, where Rbond signifies resistive impedance from the bonding effect. The noise figure (NF) analysis is not changed.

       1. Gain Analysis

    The transformed source impedance Zst can be written as:

    image

    Therefore, the Q of the circuit can be written as:

    image

    where ω0 is the series resonance frequency, Cin is the equivalent input capacitance (equal to Ctot when the Xst is in the inductive region, and equal to Ctot//Cst when the Xst is in the capacitive region and Cst is an equal capacitance to Xst), and Rl,g is the inductor resistance. If the transmission line is assumed to be lossless, then power is conserved. The input passive network voltage gain Av is calculated as:

    image

    Fig. 3 shows that the Q and voltage gain are related to the resistance part of the source impedance.

    The calculated Q and Av are compared with the Q and Av of the L-CS LNA as follows:

    image

    and

    image

    where QL-CS is Q of the L-CS LNA and Av,L-CS is Av of the L-CS LNA.

    Eqs. (4) and (5) indicate that the HQ-LNA can have a much higher Q and voltage gain than the L-CS LNA if the source impedance RS (usually 50 Ω) is much higher than the inductor resistance, and this is correct under several GHz ranges.

       2. Harmonic Rejection Ratio Analysis

    The third HR ratio can be calculated in a similar manner to the gain analysis. The third HR ratio is shown as:

    image

    where Rst3rd is the resistive part of the transformed source impedance at the third harmonic frequency. This equation reveals that if the reactance part is much larger than the Rst3rd, then large Lg, small Rst, or small Rst3rd makes high HR.

       3. Noise Figure Analysis

    Gain and HR are important factors in an LNA. The derived equations show that gain is maximized when Rst equals Rl,g (usually under several ohms). However, the NF is also an important factor in an LNA, and an optimum Rst value exists for the minimum NF. The noise factor can be calculated in a similar manner to that shown in [10-12]:

    image

    where

    image
    image

    Here, ωT is the unity gain frequency (equal to gm/Cgs), gd0 is the zero-bias drain conductance of the device, γ is the coefficient of the channel thermal noise, α is the ratio between the device transconductance and the zero-bias drain conductance, δ is the factor of the induced gate noise, and c is the correlation coefficient between the induced gate noise and the drain noise.

    From (8), the optimum source impedance, Rst _Fmin, can be determined:

    image

    As the Rst of the source impedance decreases to a given point, the noise factor decreases due to the increased gain suppressing the MOSFET channel noise. However, as the resistive part of the source impedance decreases beyond a given point, the inductor resistance and the induced gate noise become the dominant noise sources, and they increase. The optimum Rst depends on the process, bias, and resistance of the inductor.

    Ⅲ. HQ-LNA IMPLEMENTATION

    A HQ-LNA was designed and implemented using 0.13-μm CMOS technology, as shown in Figs. 4 and 5. The amplifiers had cascode configurations to improve the reverse isolation and reduce the Miller capacitance between the gate and the drain of the transistor, M1. The LNA was biased at 8 mA with a 1.2-V supply. The transistor size was carefully chosen. A large transistor consumes a great deal of power and generates large gate-source capacitances. On the other hand, a small transistor can easily suffer from other parasitic capacitances, including pad capacitance and routing capacitances. The active region of this chip is 270 μm × 450 μm, excluding pads size.

    Next, the proper transmission line was chosen. A 24.8-Ω characteristic impedance with 3.7 cm length line was selected to transform the source impedance, RS, which was 50 Ω, to 15.5, 14.4, 13.0, and 12.1 Ω at 0.64, 0.70, 0.82, and 1.07 GHz, respectively.

    The inductor, Lg, and the capacitors, C1 and C2, were chosen to generate series resonance at the above-mentioned frequencies. In our case, the inductor and capacitors were 39 nH, 0.6 pF, and 1.1 pF, respectively. The switches, S1 and S2, were implemented by MOSFET.

    Finally, the load stage was composed of only a 50 Ω resistor for measurement. This creates a low gain; however, it rarely contributes to the gain-frequency relation. Therefore, it will not interrupt the verification of the high Q resonance technique. In a practical case, the load stage can be composed of a wideband resonance circuit or high value resistor, and this provides more gain.

    Fig. 6 and Table 1 show the simulation results for the HQ-LNA and the conventional L-CS LNA. They have the same architecture (cascade), same transistor size (width and length), same bias voltage (0.67 V), and same supply voltage (1.2 V); only the input matching part is different. The HQ-LNA SW11 mode is compared with the L-CS LNA, and the HQ-LNA exhibited higher gain, higher HR, and lower NF.

    In the analysis, the Rst decreased as with the gain and the HR increased as. The simulation results show that. Moreover, as predicted, the SW00 mode NF increased dramatically because the Rst decreased beyond the optimal value for the minimum NF. In this region, the inductor resistance noise and the gate-induced noise became dominant noise sources.

    Ⅳ. MEASUREMENT RESULTS

    Fig. 7 shows the measured scattering (S) parameters. Series resonance occurred at 0.64, 0.71, 0.83, and 1.07 GHz, corresponding to the SW11, SW10, SW01, and SW00 modes, respectively. The measured S21s of the LNA were 12.1, 13.2, 15.4, and 17.4 dB at each resonance frequency with the corresponding SW modes. The measured S22s were well below -10 dB when the frequency was higher than 0.4 GHz, indicating that the load stage has little effect on S21 when the frequency is higher than 0.4 GHz. Fig. 8 shows the measured NFs. The measured NFs were 2.7, 2.9, 2.8, and 3.3 dB in the SW11, SW10, SW01, and SW00 modes, respectively. The measured third HR ratios are over 30 dB at each mode. The achieved maximum third HR ratio is 43 dB at SW00 mode. These high third HR ratios will relax the specification of the filter design for an SDR receiver. The gain, NF, and HR results were well matched with the analysis and simulation results.

    Linearity was measured by two tone input signals, which are separated 1MHz from the center frequency at the upper and lower sides in each operating mode. The measured IIP3s were -5.7, -6.1, -8, and -10.8 dBm in the SW11, SW10, SW01, and SW00 modes, respectively.

    For comparison, Table 2 gives a summary of the measured results of operation frequency, NF, and third HR for several LNAs. A wideband LNA in [3] does not provide third HR. The SW00 mode achieves the highest third HR ratio. HQ-LNA has slightly lower gain, due to it uses 130-nm CMOS process and load stage consists of pure 50 Ω resistor. This 50 Ω resistor load provides more precise observation about input network effects; however, it provides low gain. In practice, a load can consist of a resonance circuit or a higher resistor, and it can provide more gain.

    V. CONCLUSION

    In this paper, we presented a high Q input series resoance LNA to obtain high voltage gain, a high HR ratio, and low NF, as well as to support multiband operation for an SDR receiver. This technique was simply achieved by exploiting switchable capacitor banks, one inductor, and a transmission line. The high HR will relax the specification of the filter when using a hard-switching mixer.

    These effects were demonstrated by measurement of the implemented LNA. The LNA supports four operation bands (0.64, 0.71, 0.83, and 1.07 GHz) with high forward gain (12.1, 13.2, 15.4, and 17.4 dB), low NF (2.7, 2.9, 2.8, and 3.3 dB), high third HR ratios (32, 32, 35, and 43 dB), and low power consumption (9.6 mW with 1.2 V). The proposed technique is a promising option for high-performance, low-cost SDR receivers.

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  • [Fig. 1.] Simplified schematic of the high Q series resonance lownoise amplifier input network.
    Simplified schematic of the high Q series resonance lownoise amplifier input network.
  • [Fig. 2.] The equivalent input circuit of the high Q series resonance low-noise amplifier.
    The equivalent input circuit of the high Q series resonance low-noise amplifier.
  • [Fig. 3.] Calculated Q and input network voltage gain Av versus the resistance part of the source impedance, Rst. (The Ctot = 0.56 pF and Rl,g = 5 Ω are assumed. w0 = 1.07 GHz).
    Calculated Q and input network voltage gain Av versus the resistance part of the source impedance, Rst. (The Ctot = 0.56 pF and Rl,g = 5 Ω are assumed. w0 = 1.07 GHz).
  • [Fig. 4.] Complete schematic of the LNA with the proposed technique.
    Complete schematic of the LNA with the proposed technique.
  • [Fig. 5.] (a) Chip photograph of the low-noise amplifier (LNA) and (b) photograph of the fabricated LNA on the printed circuit board.
    (a) Chip photograph of the low-noise amplifier (LNA) and (b) photograph of the fabricated LNA on the printed circuit board.
  • [Fig. 6.] Simulated gain of the high Q series resonance low-noise amplifier (HQ-LNA) and conventional the inductively degenerated low-noise amplifier (L-CS LNA).
    Simulated gain of the high Q series resonance low-noise amplifier (HQ-LNA) and conventional the inductively degenerated low-noise amplifier (L-CS LNA).
  • [Table 1.] The HQ-LNA and conventional L-CS LNA simulation results
    The HQ-LNA and conventional L-CS LNA simulation results
  • [Table 2.] Comparative summary about the frequency, NF, and third HR of LNAs
    Comparative summary about the frequency, NF, and third HR of LNAs
  • [Fig. 7.] Measured S-parameters of the high Q series resonance low-noise amplifier (HQ-LNA): (a) S21, (b) S11, (c) S12, and (d) S22.
    Measured S-parameters of the high Q series resonance low-noise amplifier (HQ-LNA): (a) S21, (b) S11, (c) S12, and (d) S22.
  • [Fig. 8.] Measured noise figure of the high Q series resonance low-noise amplifier (HQ-LNA).
    Measured noise figure of the high Q series resonance low-noise amplifier (HQ-LNA).